Chip Power Breakthrough Reported by Startup

Carl Bialik from WSJ writes "The Wall Street Journal reports that a tiny Silicon Valley firm, Multigig, is proposing a novel way to synchronize the operations of computer chips, addressing power-consumption problems facing the semiconductor industry. From the article: 'John Wood, a British engineer who founded Multigig in 2000, devised an approach that involves sending electrical signals around square loop structures, said Haris Basit, Multigig's chief operating officer. The regular rotation works like the tick of a conventional clock, while most of the electrical power is recycled, he said. The technology can achieve 75% power savings over conventional clocking approaches, the company says.'"

Article text for the hard-of-linking

Chip Power Breakthrough Reported
By DON CLARK
May 8, 2006; Page B6

A tiny Silicon Valley company is proposing a novel way to synchronize the operations of computer chips, addressing power-consumption problems that are a major issue facing the semiconductor industry.

Multigig Inc., a closely held start-up company in Scotts Valley, Calif., says its technology is a major advance over the clock circuitry used on many kinds of chips.

Semiconductor clocks work like the drum major in a marching band, sending out electrical pulses to keep tiny components on chips performing operations at the right time. In microprocessor chips used in computers, the frequency of those pulses -- also called clock speed -- helps determine how much computing work gets done per second.

One problem is that the energy from timing pulses flows in a one-way pattern through a chip until it is discharged, wasting most of the power. Clocks account for 50% or more of the power consumption on some chips, estimates Kenneth Pedrotti, an associate professor of electrical engineering at the University of California at Santa Cruz.

Partly for that reason, companies such as Intel Corp. have all but stopped increasing the clock speeds of microprocessors, a popular way to increase computing performance through most of the 1990s.

John Wood, a British engineer who founded Multigig in 2000, devised an approach that involves sending electrical signals around square loop structures, said Haris Basit, Multigig's chief operating officer. The regular rotation works like the tick of a conventional clock, while most of the electrical power is recycled, he said. The technology can achieve 75% power savings over conventional clocking approaches, the company says.

A typical chip would use an array of timing loops, in a grid akin to a piece of graph paper, Mr. Basit said. The loops automatically synchronize their timing pulses. That feature helps address a problem called "skew" -- the slightly different arrival times of timing pulses throughout a typical chip -- that tends to limit clock precision.

Multigig says its self-synchronizing loops can run efficiently at unusually high frequencies.

Mr. Pedrotti said past attempts to address the skew problem have tended to increase power consumption. He and his students, some of whom receive research funding from Multigig, have performed simulations that so far back up the company's claims, though the team is just about to start tests using actual chips, he said.

Multigig is in talks to license its technology to chip makers, as well as design some of its own products to use the clock technology. Besides microprocessors and other digital chips, the approach could help synchronize frequencies of communication chips, Mr. Basit said.

"This is a dramatic way of clocking circuits," said Steve Ohr, an analyst at Gartner Inc. He cautioned it could take years to get existing manufacturers to modify existing products to take advantage of the new technology. "Intel is not going to redesign the Pentium tomorrow because of it," he said.

Re:I'll call bullshit

Clock skew impacts your timing margin (If you've got 2 flip flops that in theory see the clock at the same instant, any uncertainty in the clock arriving will inpact your timing from one to the other). One concequence of this is you often have to have larger faster drivers on both your clock tree and your logic to work around this timing problem.
Larger drivers = larger power.

Therefore if you've got a method to make your clocks arrive more accuratly then you've more timing margin between FFs and therfore can use smaller drivers.

Clock trees are also the major consumer of power in most designs, so anything that can reduce them is good.

Async removes the clock altogether so you save power there.

So yes both of them can be right.

This is a breakthrough!

Conventional electronics uses circular loop structures to send electrical signals as the electrons would get caught on corners that were too sharp. These people must have overcome that limitation.

Not so fast

He cautioned it could take years to get existing manufacturers to modify existing products to take advantage of the new technology.

D'oh! Looks like I won't be getting 12 hour battery life on my laptop anytime soon!

Simple Math

So "up to" 75% savings on "up to" 50% of the electricity usage. So 3/8 or 37.5% savings, all in all... Of course this is only for the CPU... Could be noticeable in production... Maybe...

Advertising lingo - "up to"

Remember, in advertising-speak, "up to" means "less than". Values between 0% and 75% fulfill the conditions of being "up to a 75% savings".

Radical Breakthrough?

"Intel is not going to redesign the Pentium tomorrow because of it," he said.

Why not? If this works it sounds like Moore's law would continue, and would give whatever company that deployed it first a performance advantage.

Is this really so radical we'll have to wait years to get it on our desks?

Re:Radical Breakthrough?

Why not? If this works it sounds like Moore's law would continue, and would give whatever company that deployed it first a performance advantage.

Because first they're going to get a bunch of their theoreticians to work the math on the problem to make sure it's viable. Then they're going to get a bunch of their VLSI modellers to run virtual simulations on the clock modification to refine exactly how great the potential efficiency gain would be. If that turns out OK then they'd produce some simple mock-ups of the new clock architecture to make sure that it functions correctly in hardware. Then they'd go about the expensive and time-consuming process of redesigning the current chip architectures to include the new style clock. Then they'd produce an initial fabrication of the chip to run through extensive hardware testing (and on the inevitable failure they'd hop two steps back and try again.) Once they were happy with the design they'd scale up to full production and roll it out.

Everybody in the microprocessor design world remembers this [wikipedia.org] all too well.

Getting closer

We're getting ever closer to the perpetual motion machine, just 25% energy savings to go ;-)

Seriously though, I'll look forward to seeing this new chip in production, since more energy efficient chips means less waste heat, and thus quieter computers with fewer fans. I'll trust it when I see it, I'm not so swayed by a company that is still just a "startup" probably looking to get a boost to its stock price by anouncing a breakthrough.

You might save a lot of power

Most of the power in a computer is used once and wasted. The input to a gate acts like a capacitor. When the input is driven from a zero to a one, the current is limited by the resistance of the output gate driving it. That resistance is where the power is dissipated. The charge is drained to ground when the input is driven from a one to a zero. If there was some way to re-use the charge stored in the inputs, the power dissipation of a chip could be dramatically reduced. There would be a limit to how much efficiency could be gained but we haven't done anything about it yet. One of the major limits to chip performance is heat and doing something like this would help to keep Moore's law valid.

No overclocking

You can't readily adjust the amount of time it takes electricity to make its way around a fixed-size loop. If this is what is actually clocking the chip, it'll have an official frequency (or two, perhaps, for low-power usage) and you'll be stuck with that. The manufacturer would have to throw out, rather than derate, any parts that don't work at that frequency.

Chip technology is awesome

Ok nerds, tell me if this is feasible....

First of all, I can barely grasp how chips work in the first place, lots of yes-no-maybe so gates that the electrons have to pass through.

So, would it be possible to make a 3-D chip? Where, instead of one line or branches that the electron follows but a crazy ass network for it to flow through?

Re:Chip technology is awesome

Ok nerds, tell me if this is feasible....

P.S. In this context, the correct spelling of nerd is E-N-G-I-N-E-E-R ;^)

So, would it be possible to make a 3-D chip? Where, instead of one line or branches that the electron follows but a crazy ass network for it to flow through?

In most respects, chips today are ALREADY 3d in that there are multiple layers of planar (flat layers) metal wiring (anywhere from 4 to 8) connected by vias (vertical interconnect) over a single layer transistors. The routing of signals on each layer is on purpose designed to be a crazy-ass network (to avoid electromagnetic signal coupling noise between adjacent wires).

However, in current technology, there's still only 1 layer of transistors, and the main limitation of adding more is that there's no good way to get rid of the heat of transistors. Even today, there isn't a good way to get rid of the heat of the transistors in the 1 layer of current chips, let alone a big pancake stack (or lasagna) of transistors. People are already starting to stack memory chips that don't get too hot together, and I'm sure they'll eventually start doing different kind of stacks too as they get better at figuring out the heat problem...

Sounds good but what about size?

Like with asynchronous processors, maybe its downside will be the silicon area required to implement it.

Other techniques like multiple independant clock areas that can be shut down when not in use seem far more beneficial, IMHO.

less power consumption for your berserker!

This will go well with the robotic tentacles. Now your berserker can use even less power, reserving more for the really critical things like the LASER (we need a /. article on military LASERS).

vaporware...?

It just amazes me that a small, never-before-heard-of-company offers a solution to a problem that Intel, IBM, and AMD have been trying to solve for over a decade, each of which have 10 times the budget, expertise, and personel. Did I mention a headstart of a minimum of 10 years of R&D tossed at this problem? I hate to be a pessimistic troll-like poster, but without even a working proof of concept, I can only call this vaporware until they show me a working product. This article says nothing except "we have technology every computer in the world will need in the next ten years... please invest in us and we'll get you a demo soon."

Re:vaporware...?

It just amazes me that a small, never-before-heard-of-company offers a solution to a problem that Intel, IBM, and AMD have been trying to solve for over a decade, each of which have 10 times the budget, expertise, and personel.

I'm in no way qualified to comment on the actual technology here, but I will submit that this situation isn't as unlikely as it might seem. For many problems, the potential solution-space is so large (and the cost of trying out various approaches is so significant) that even a large R&D lab with a big budget and years of effort can end up missing what in retrospect is a very clever and useful solution. It's easy to get bogged down trying "just one more tweak" of your first (or second or third) approach that you never look around and notice the other approach hiding in plain sight. Even worse, a given organization can easily build up a culture that says "this is the way we do things, because this is the way we know things work", which can discourage even bright new employees from looking at alternative methods. (i.e. Why "start from scratch" with approach B when your company has invested millions in developing approach A?)

A new startup, on the other hand, doesn't have all that baggage that might limit their point of view. Or even more likely, some bright person may have had The Big Idea, and decided to found a startup to exploit it and get rich, rather than donating his idea to some pre-existing corporation.

That said, there is plenty of room for bullshit vaporware in the world too :^)

Induction feedback ...

An impossible concept only invented like a hundred years ago. Next, they will be charging things known as capacitors from the induced current.

Technical paper?

Is there a technical paper on this? I know it's probably patented and they want to keep as much detail as possible but it seems like a somewhat abstract paper of how this works would convince the chip makers they want to sell this to to be interested. And satisfy curious people like me.

Re:Technical paper?

The press has a knack for distorting stories and making it very hard to figure out real technical details.

http://multigig.com/pub.html [multigig.com] has some whitepapers. I read the ISSCC 2006 slide set, which let me know the general technique.

Basically, they produce a clock ring to produce a "differential" clock pair that after one lap swaps neg and pos and so it's frequency is tuned by it's own capacitance and inductance. They call it a "moebius" loop since it's not really a differential pair, but the clock wave makes two round trips before getting back to the start.. Neighboring loops can be tuned together (although if that's by just routing the wave throughout the chip I'm not sure). They didn't seem to mention synchronizing the period to outside sources, and I'm not sure how they'll be able to do that.

The clocking is not the interesting part to me, but rather their logic strategy. The trick is that logic itself has no connection to power or ground. The clock nets provides the "power and ground" and all logic must be done as differential (a and abar as inputs, q and qbar as outputs). This is where they get the power savings from--the swings are reduced and there's no path to power or ground to drain away charge. Without really discussing it, charge seems to just shift around on internal nodes between the differential logic states. They then use pure NMOS fets for logic, which removes all PMOS. The logic will never read the power rail, though--it will always be a Vt drop. I just looked this over quickly, but it seems the full-swing clocks and lack of PMOS make this work out fine.

For quick adoption, they'll need to work out clever techniques to connect this logic to standard clocked logic. Otherwise, it looks only a little bit easier to use than asynchronous logic. The issues they face seem very similar to asynchronous logic issues--tool support, interface to standard clocked logic, debug, test, etc.

It's not vapor.

I call BS

I've read the FA and despite having a couple of CMOS designs behind me I don't understand a bit of what they are saying. Either the reporter that wrote this has absolutely no idea what he is writing or this entire 'breaktrough' is just vapourware.

The article seems to say that the 'tick' of the clock is carrying energy throughout the chip and when the 'tick' hits the edge, the energy is lost. Electronics in your typical digital circuit does not work that way. Energy does not flow through the chip with the signals (ok, it does theoretically, but that amount is negliable with the dynamic losses in the gates mentioned below).

You get power dissipation in each gate or buffer that changes state because of some signal, irregardless of the direction in which the information is flowing. You can not recycle this power. This comes directly from the basic principle behind CMOS technology (used by almost all digital chips today) - you are charging and discharging a capacitor.

Typical example, that running signals in a circuit does not save power: take a ring oscillator (a number of negators wired in a loop). This circuit will oscillate (send changing signals through its loop) and consume an considerable amount of power.

Re:I call BS

Better link here

http://www.eetimes.com/news/latest/showArticle.jht ml?articleID=187200783 [eetimes.com]

Looks interesting. I wonder what they mean with 'taps', and if they calculated their power savings right (would each register need its own tap, or if not, is the buffer needed to boost the power from the loop included in the clock system power?)

Re:I call BS

You get power dissipation in each gate or buffer that changes state because of some signal, irregardless of the direction in which the information is flowing. You can not recycle this power. This comes directly from the basic principle behind CMOS technology (used by almost all digital chips today) - you are charging and discharging a capacitor.

You're half right. You're right that what's going on is a charging and discharging of a cap, but you're wrong that the charge can't be recycled. A conventional clock works by connecting the gates of a bunch of devices (i.e. capacitance) to Vdd, then after a little time connecting it to ground instead. Wait a little bit, then repeat. What effectively happens is that you dump some amount of charge from Vdd to ground each switch, and it's gone (i.e. it's heat now). A water analogy would be a tub of water above you (Vdd), a bucket in your hand (the capacitance), and the ground (gnd). You pour some water from the tub into your bucket (charge the cap), then dump it on the ground.

It doesn't have to be this way. There are actually ways to charge a capacitor, and then pull the charge back out again (without dumping it to ground)! I'm going to assume you're familiar with LRC circuts, and how they can resonant when an impulse is applied. What's going on during the oscilattions? Charge is moving into the capacitor, and then being pulled back out to the inductor. The same charge goes back and forth, ideally forever (of course, in practice, the resistance isn't 0 so you put out some heat and the oscillations dies down). I'm not sure what exactly the water analogy would be - maybe a wave sloshing back and forth in a trough.

I recently attended a seminar where the presenter talked about clocking based on LRC oscillations and he had actually fabbed chips that worked. The basic idea was to put an inductor on the die, and set up oscillations between the inductor and the clock load capacitance, which results in a ticking clock. Of course, you get a sinusoidal clock instead of a nice almost-square-wave, so your circuits have to be designed a little bit differently, but the point is, it works and is doable.

Now, the technology described in this article, as best as I can tell, uses another idea - transmission lines. In a normal design, your clock grid basically looks like a bunch of capacitors with resistors in between (i.e. distributed RC). It takes time for a signal to propagate - signals propagate much slower than the speed of light, becuase you actually have to charge up the capacitance along the line through the resistance of the line itself. Imagine a long trough that's empty. You start pouring water in, and although water reaches the far side pretty quickly, you don't actually observe it until the water level at the far end is half way up. Signals propagate differently when wires are set up as transmission lines - they propagate at much closer to the speed of light, because you're actually sending a wave down the line (imagine creating a ripple on a trough of water, instead of actually filling and emptying the trough).

Now, I don't understand how they combined charge recycling and transmission lines, I don't understand transmission lines all that well, but your arguments aren't good reasons to disregard the claims made by the company.

If you're interested, here [cmu.edu] is a little bit of info about the talk I went to.

Typical example, that running signals in a circuit does not save power: take a ring oscillator (a number of negators wired in a loop). This circuit will oscillate (send changing signals through its loop) and consume an considerable amount of power.
If you created an oscillator between an inductor and a capacitor, on the other hand, once you started it going, it would continue for a long time with minimal energy injected in the future.

Voltage flowing in loops..

What a breakthrough [wikipedia.org]

Well now...

I think I can decrease my gas consumption by up to 75% by throwing square wheels on my car! Of course the reason would be because i would be 75% less likely to use a car that really cant go anywhere.

Clockless CPUs?

Since clocks take up a large percentage of the power and space on the chips, why not do away with them? Why not use a clockless CPU so results are available as soon as they are ready? There are some processors out there (ARM Amulet for instance) that do this, does it just not scale well to the high speeds we are used to now on our desks and laps, or is it just that current clocking cpu design is way ahead in terms of development?

Sounds like my 84 RX-7

Design sounds similar to the motor in my 84 RX7

Good idea, but how useful is it?

It appears basically that they make a clock loop just long enought to get a clock skew of 360 degrees, and connect back to itself.

Now you can get any clock skew you want just by picking the clock off at the right place in the loop.So circuits with a skew requirement must be at just the right location along the ring.

I can see how this can be anadvantage in fast small circuits like an ADC.

How can this be any advantage on a complex circuit? It appears:
0. The clock loop will impose a lot of layout restrictions on the circuit.
1. you will need a tree of these loops just like a clock tree.
2. The IC has a fixed clock. So initial bringup must be done at maximum frequency. What a nightmare that might be.(Note that the only purpose for using this is to enable as high speed and little jitter as possible.) Does it imply a full layout change every time you try to up the clock frequency?

Notice that the Gartner group financial analyst calls it almost a "perpetuum mobile"

resonator?

It's a little bit hard to tell from the article (the eetimes one is better), but it sounds like they're using the ring as a resonator to carry the clock. Ring resonators aren't exactly new (especially in my field, waveguide optics), but using them as clocks poses a few interesting challenges. If you extract energy (signal), you're going to damp out the resonator; if you couple multiple loops, for carrying the clock to internal points in the circuit, you need to ensure that the resonator frequencies are exactly matched. Doing this for a couple of resonators isn't hard. Doing it for the hundreds you'd need for a CPU sounds bloody well impossible. You'd have to actively detect and correct for phase error at each coupling point, adding lots of RF analog electronics, which would suck.

EETimes: Xmas gift leads to rotary wave epiphany

In addition to the already cited

http://www.eetimes.com/news/latest/showArticle.jht ml;jsessionid=SG3NCFVRB3QWEQSNDBESKHA?articleID=18 7200783 [eetimes.com]

the EE Times piece (in the printed edition not up on the web) has a sidebar,
with neat background on the inventor:
________

Christmas present leads to ratoary wave epiphany

          The Rotary Traveling Wave technology was the brainchild of MultiGig Inc.
founder and chief technology officer John Wood, a self-taught inventor
and son of an inventor who developed a method for self-aligning installed
underground water pipes. In a company filled with PhDs, Wood is the only
employee without a college degree.

          Wood earned millions from a patent on this technique for flash-welding
plastic materials. His passion for technology drives him to order textbooks
by the dozen when pursuing a new subject, sometimes noting their errors in
scribbled notes in the margins, said MultiGig COO Haris Basit. "I've worked at
research labs including Yorktown Heights and Bell Labs, and John is clearly
a cut above," Basit said.

          In the late 1990s, Wood was researching high-speed serial I/O using
traditional ring and crystal oscillators. "As I started to explore alternatives,
the first thing I looked at was transmission times," he said.

          An intitial prototype, using coaxial cables, was "not very exciting."
Then Christmas 1998 brought an ephiphany. "My son had just gotten a
car racing game with a crossover on a single track. That gave me the idea
for arranging the transmission line that way," said Wood.

          After a few more months of work, Wood decided to use arrays of loops
to create an approach that could work independently of any frequency
or process technology.

          "It took a year or two until we could find direct commercial applications.
Before that, I was just working on it as hobby." said Wood. "But the more we
looked at clock distribution, the more we realized this could be useful."

-- Rick Merritt

Clockless systems even faster?

I read somewhere here on Slashdot as I recall about clockless CPUs and system designs. Why are people still working with clocked computers and technology if clockless holds so much promise?

great inventions

If this thing works, and it sounds to me that it does, it could be the next breakthrough.

Jot it down in the list of great inventions from start-ups, which big companies have not been able to achieve. I'm sure the big-companies would not have thought out-of-the-box for an approach like this. only start-ups can "afford" to do such a thing ;)

low power computing

This remind me of low-power reversible computing that I learned back in college from Prof. Jan van de Snepscheut at Caltech... The basic idea is to reduce wasted power by "sloshing" current within the chip, rather than to let the current spill to the ground... (this is a a gross simplification...)

This (highly technical) paper describes what I'm talking about:
http://www.zyvex.com/nanotech/electroTextOnly.html [zyvex.com]

This article mentions a "helical logic" which sounds a bit like what this invention is...

Ob www.timecube.com reference

sending electrical signals around square loop structures ... the electrical power is recycled ... the technology can achieve 75% power savings

And I thought P = VI.

But of course! I am educated stupid. According to NATURE'S HARMONIC SIMULTANEOUS 4-DAY TIME CUBE, the opposite hemispheres cancel out. Earth exist as 4 - 90 degree opposite corner quadrants, but not to a 360 degree circle... [timecube.com]

Rule Britannia!

As usual, it seems that a useful British invention is being promoted and developed in America.

We still have lots of good inventors, but they either get no backing, or have to go abroad, or either watch their idea dieing, or being exploited by someone else.

It's no wonder our country is going to pot. You need to be on a TV reality show to be successful these days.

ISSCC paper describing Multigig technology

Is this real??? check out the Multigig web site... I noticed that Multigig has multiple papers on their technology. http://multigig.com/publications/DRAFT_ISSCC_2006_ PAPER.pdf [multigig.com] Multigig comments on multiple application use for Clock trees, RF and analog. I noticed a paper on analog applications at http://www.oea.com/document/DesignConPaper_04.pdf [oea.com] but the most interesting is a copy of an ISSCC paper at UCSD? http://www-cse.ucsd.edu/classes/wi06/cse291-b/slid e/let8/rotary.pdf [ucsd.edu]

Re:nah

agreed... especially when I read parts of TFA like this:

" Multigig, have performed simulations that so far back up the company's claims, though the team is just about to start tests using actual chips, he said. "

Given lots of unknown factors that can arise when you're using real electrons on real silicon, I like the idea, but I'll happily wait for the prototype before thinking this would be a net good thing.

/P

Re:nah

Are you saying regenerative braking doesn't exist?

Re:nah

I share your doubts, but must point out that current hybrid cars already use regenerative [toyota.com] braking [honda.com]. The efficiency is only something like 30% (losses to transmit through the CVT, generate, store, spin the motor again), but it's still a little bit of return. Since the motor is already designed to act as a generator, it should be little extra investment to program the transmission to load the motor before mechanically engaging the brakes.

Re:EMI

No more than any other high-speed, spiking digital signals.