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Micro-Pump is Cool Idea for Future Computer Chips
Posted by
ScuttleMonkey
on Wed Apr 26, 2006 07:29 PM
from the bad-pun-already-in-the-headline dept.
from the bad-pun-already-in-the-headline dept.
core plexus writes to tell us that Engineers at Purdue University have designed a tiny 'micro-pump' cooling device that can be used to circulate coolant through the channels etched on an individual chip. From the article: "The prototype chip contains numerous water-filled micro-channels, grooves about 100 microns wide, or about the width of a human hair. The channels are covered with a series of hundreds of electrodes, electronic devices that receive varying voltage pulses in such a way that a traveling electric field is created in each channel. The traveling field creates ions, or electrically charged atoms and molecules, which are dragged along by the moving field."
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Not exactly one for the modders (Score:3, Insightful)
Re:Not exactly one for the modders (Score:2)
The way I see this working is having the micropump embedded INSIDE the chip so the surface can be attached to a heatsink and dissipate heat more efficiently.
Re:Not exactly one for the modders (Score:3, Insightful)
Cooling channels allow chip fabrication in 3D! (Score:5, Interesting)
Re:Cooling channels allow chip fabrication in 3D! (Score:2)
Re:Cooling channels allow chip fabrication in 3D! (Score:4, Insightful)
I'd say the solution to it would be to lay out the cooling channels just like other routes in the die, and set the parameters up somehow in the routes would be relatively well distributed for maximum heat absorption.
Parent
Cooling is not the only problem (Score:5, Informative)
For example, one of the assumptions that exists on a semiconductor wafer before it is printed is that it is effectively flat (a typical peak to valley range on a modern wafer within the expected field of a chip is on the order of 175 to 200 nm)
Polishing to that accuracy once structures have been placed on a semiconductor wafer is difficult. Getting a consistent layer of material when you are polishing an uneven surface (uneven due to vias [connections] to the other layers of silicon present) is downright challenging. Another problem with printing transistors on anything but a pure wafer is the issue of reflection. Thin layers of materials on a semiconductor are semi-transparent and not perfectly vertical. Those angled and curved structures produce reflections. Those reflections can cause problems in printing later layers (because of constructive and destructive interference of the light used to expose the photoresist). Those reflections mean that modeling the exposore process of a 3D semiconductor is a VERY challenging task.
Such items are not of concern today, because the later structures placed on the wafer are generally metal lines or capacitors for DRAMs or lenses for image sensors, etc. These are all large and some level of imprecision is acceptable. While variation can cause differnet RC characteristics in metal lines, the timing models in the library or other models can account for this variation. In fact, Matrix Semiconductor has been producing 3D DRAM since about 2004, which shows that heat isn't necessarily the problem, and DRAMs (and memory in general) are a reasonable application for 3D technologies (likely because the capacitors are generally large in relative terms).
Transistors, however, are much more sensitive to variation, and the variation in later polishing used today is too rough for the effective printing of transistors. While I don't doubt that there are situations where the density will be valuable, I think 3D processors and custom chips (in consumer electronics, et al.) are as much an economic issue as a cooling/technical one. (in other words, with my understanding of current roadmaps, you will decrease semiconductor yield to such a degree that 3D may not be economically viable, even if the cooling problem is solved.)
Parent
Re:Cooling is not the only problem (Score:4, Funny)
"Your CMOS-fu is greater than mine! Please say more, so that I might sit and listen!"
Can you point to some more links on 3D fabrication? Thanks!
Parent
Clarification and more information on 3D (Score:3, Informative)
No physicist am I, but... (Score:2)
Wouldn't this impact performance or timing issues within the chip?
Re:No physicist am I, but... (Score:2)
But you're right, it would cause issues if they were actually using them for signals, but it's simply so they can move the coolant around.
Re:No physicist am I, but... (Score:2)
Re:No physicist am I, but... (Score:2)
Having said that however, it seems that doing this would seriously complicate chip design as most of the actual work in chip design is dealing with electromagnetic concerns.
seems like this would be juju of the worst kind.
Channels of coolant, or just heat conductor? (Score:2)
Re:Channels of coolant, or just heat conductor? (Score:2)
Re:Channels of coolant, or just heat conductor? (Score:4, Informative)
A conductor would have to be thick, which would take up a lot of space.
Moving s liquid with high heat capacity (such as water, which has ENORMOUS heat capacity) means you can move the heat out by transporting the liquid, rather than by conducting the heat THROUGH it. The liquid can then drop off the heat at the heat sink in a leisurely fashion on its way through. Heat only has to move by conduction across distances measured in molecular diameters rather than inches.
Parent
Whole new meaning to processor blocking (Score:5, Funny)
Re:Whole new meaning to processor blocking (Score:4, Funny)
Parent
Sounds Cool (Score:2)
Having wet, electically charged canals in the middle of a CPU sounds weird upon reflection. And aren't they huge compared to the circuits, where's the room?
hmm
Article says challenges include sealing it to prevent leaks...DUH.
Nor did they say the chip included OTHER circuits yet...THE WHOLE REASON for this cooling to exist.
Interesting idea, nothing more and won't be for some time.
I slightly misunderstood the teaser (Score:5, Informative)
This system works in multiple ways, it has an ionisation pulse that travels along the water lines
The pulse ionizes the water the ionized water is dragged by the pulse
the pulse alters the shape of a small membrane, boosting the pump.
as for the efficiency that being said, it's still work in progress, and they (according to the article) haven't solved leakage problems yet.
From plants (Score:4, Informative)
Link: http://www.cas.muohio.edu/~meicenrd/ANATOMY/Ch9_T
I have a better idea. . . (Score:4, Interesting)
KISS (Keep It Simple, Stupid) -- they're over-complicating the solution. Fluid directly in the chip might be a good idea, but let conduction and natural convection handle the heat transfer to the heat spreader. Don't over-complicate this thing with a pump that can break the second a nanometer particle gets into the system.
Electric fields strong enough to push particles... (Score:3, Insightful)
So very appropriate (Score:3, Funny)
[crickets...]
Pointless for desktop PCs (Score:3, Interesting)
Except for supercomputers, servers, and hard-core gamers with air conditioning, who is going to want chips that will generate substantially more heat than current chips? If CPUs alone start using hundreds of watts of power, people are going to take notice, and even the most naive shopper will start taking this into account. Already, Intel has realized [wikipedia.org] that their ridiculous space heaters are a dead end.