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Micro-Pump is Cool Idea for Future Computer Chips

Posted by ScuttleMonkey on Wed Apr 26, 2006 07:29 PM
from the bad-pun-already-in-the-headline dept.
core plexus writes to tell us that Engineers at Purdue University have designed a tiny 'micro-pump' cooling device that can be used to circulate coolant through the channels etched on an individual chip. From the article: "The prototype chip contains numerous water-filled micro-channels, grooves about 100 microns wide, or about the width of a human hair. The channels are covered with a series of hundreds of electrodes, electronic devices that receive varying voltage pulses in such a way that a traveling electric field is created in each channel. The traveling field creates ions, or electrically charged atoms and molecules, which are dragged along by the moving field."
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  • Not exactly one for the modders (Score:3, Insightful)

    by Anonymous Coward on Wednesday April 26 2006, @07:33PM (#15208698)
    The smallest particle in the coolant would block it.
    • The coolant is supposed to be built in, doh.

      The way I see this working is having the micropump embedded INSIDE the chip so the surface can be attached to a heatsink and dissipate heat more efficiently.
    • True, in fact it's a kind of catch-22. Dirty water is more conductive than clean water. Using an EHD drive to pump the water is ingenious, but if the water's too clean it won't efficiently pump through the channels, if it's even slightly dirty, there will
  • by jlseagull (106472) on Wednesday April 26 2006, @07:34PM (#15208705) Homepage
    Chips fabbed in 3D have numerous advantages - short trace lengths, higher density, etc. However, the problem with all of them is getting the heat out with today's convective cooling technologies. This technology will allow multiple cores in 3D to operate without overheating, and that's a good thing as the number of cores in personal computers and servers continues to increase.
    • Eh? But wouldn't it be more difficult to deal with the silicon in three dimensions? I'm not an engineer, but I imagine that the wafers are much easiers to use, (especially with my understanding of how they create transistors using semi-conductors).
      • by ShakaUVM (157947) on Wednesday April 26 2006, @08:18PM (#15208931) Homepage Journal
        The trouble is that routing on chips isn't done by hand anymore. An algorithm crunches away on a design and spits out what it found to be the most optimal layout for the given parameters. So if you have to start pushing things around by hand in order to make room for cooling channels, it could break your design.

        I'd say the solution to it would be to lay out the cooling channels just like other routes in the die, and set the parameters up somehow in the routes would be relatively well distributed for maximum heat absorption.
        [ Parent ]
    • Cooling is not the only problem (Score:5, Informative)

      by thpr (786837) on Wednesday April 26 2006, @08:18PM (#15208926)
      Yes, 3D is a neat application, but cooling is not the only challenge in 3D semiconductor electronics. Another perspective on 3D is available in Business Week's More life for Moore's Law [businessweek.com] article.

      For example, one of the assumptions that exists on a semiconductor wafer before it is printed is that it is effectively flat (a typical peak to valley range on a modern wafer within the expected field of a chip is on the order of 175 to 200 nm)

      Polishing to that accuracy once structures have been placed on a semiconductor wafer is difficult. Getting a consistent layer of material when you are polishing an uneven surface (uneven due to vias [connections] to the other layers of silicon present) is downright challenging. Another problem with printing transistors on anything but a pure wafer is the issue of reflection. Thin layers of materials on a semiconductor are semi-transparent and not perfectly vertical. Those angled and curved structures produce reflections. Those reflections can cause problems in printing later layers (because of constructive and destructive interference of the light used to expose the photoresist). Those reflections mean that modeling the exposore process of a 3D semiconductor is a VERY challenging task.

      Such items are not of concern today, because the later structures placed on the wafer are generally metal lines or capacitors for DRAMs or lenses for image sensors, etc. These are all large and some level of imprecision is acceptable. While variation can cause differnet RC characteristics in metal lines, the timing models in the library or other models can account for this variation. In fact, Matrix Semiconductor has been producing 3D DRAM since about 2004, which shows that heat isn't necessarily the problem, and DRAMs (and memory in general) are a reasonable application for 3D technologies (likely because the capacitors are generally large in relative terms).

      Transistors, however, are much more sensitive to variation, and the variation in later polishing used today is too rough for the effective printing of transistors. While I don't doubt that there are situations where the density will be valuable, I think 3D processors and custom chips (in consumer electronics, et al.) are as much an economic issue as a cooling/technical one. (in other words, with my understanding of current roadmaps, you will decrease semiconductor yield to such a degree that 3D may not be economically viable, even if the cooling problem is solved.)

      [ Parent ]
      • by jlseagull (106472) on Wednesday April 26 2006, @08:39PM (#15209033) Homepage
        (mouth moving out of sync with the words, as in a chop-socky flick)

        "Your CMOS-fu is greater than mine! Please say more, so that I might sit and listen!"

        Can you point to some more links on 3D fabrication? Thanks!
        [ Parent ]
        • So I did realize after I posted the grandparent comment that there are actually two different technologies at work here. I just recognize '3D' as 3D fabrication: using a single wafer and printing multiple layers of transistors. That is what I was referri
  • It seems that using a field to push ions around would create "inertia" or damping on the signal that is pushing it.
     
    Wouldn't this impact performance or timing issues within the chip?
     
    • These ions don't have anything to do with the electrical signals for computation. The ions are the coolant, so you're just simply inducing an electric field to push them along.

      But you're right, it would cause issues if they were actually using them for sig
    • At first I thought they were using the computational signals to push, but after going through the article more carefully I realized that.

      Having said that however, it seems that doing this would seriously complicate chip design as most of the actua
  • Wouldn't it be easier to do the cooling on the chip and use something that conducts heat very good on the chip? I mean, I would rather have lanes of some conductive, non moving material instead of some liquid running through my CPU, if you don't mind.
    • Yup, like copper for example. I guess that would be too simple - you can't get venture capital for adding copper bars to a chip...
    • by Ungrounded Lightning (62228) on Wednesday April 26 2006, @07:57PM (#15208828) Journal
      Wouldn't it be easier to do the cooling on the chip and use something that conducts heat very good on the chip?

      A conductor would have to be thick, which would take up a lot of space.

      Moving s liquid with high heat capacity (such as water, which has ENORMOUS heat capacity) means you can move the heat out by transporting the liquid, rather than by conducting the heat THROUGH it. The liquid can then drop off the heat at the heat sink in a leisurely fashion on its way through. Heat only has to move by conduction across distances measured in molecular diameters rather than inches.
      [ Parent ]
  • by syousef (465911) on Wednesday April 26 2006, @07:41PM (#15208736)
    ...and what's the term for a blocked CPU? Constipated???
  • ok, bad pun is outta the way :)

    Having wet, electically charged canals in the middle of a CPU sounds weird upon reflection. And aren't they huge compared to the circuits, where's the room?

    hmm

    Article says challenges include sealing it to prevent leaks...DUH.
  • I slightly misunderstood the teaser (Score:5, Informative)

    by Xiph (723935) on Wednesday April 26 2006, @07:45PM (#15208756)
    So for those of you who did the same.
    This system works in multiple ways, it has an ionisation pulse that travels along the water lines
    The pulse ionizes the water the ionized water is dragged by the pulse
    the pulse alters the shape of a small membrane, boosting the pump.
    as for the efficiency
    We have shown that the power input required is in the microwatts, but you can get milliwatts of cooling
    that being said, it's still work in progress, and they (according to the article) haven't solved leakage problems yet.
  • From plants (Score:4, Informative)

    by piotru (124109) on Wednesday April 26 2006, @07:47PM (#15208769) Homepage Journal
    Simplifying, the plants are thought to use similar idea to transport viscous liquid within their vascular system - phloem. Beautiful!
    Link: http://www.cas.muohio.edu/~meicenrd/ANATOMY/Ch9_Tr ansport/phloem.html>
  • I have a better idea. . . (Score:4, Interesting)

    by kimvette (919543) on Wednesday April 26 2006, @08:16PM (#15208918) Homepage
    Why not implement oh, I don't know, say, a Peltier Junction directly into the heat spreader? Since you KNOW there is going to be a heat sink (no warranty if no heatsink is used) then any overheating concerns from running the junction without a heat sink are moot.

    KISS (Keep It Simple, Stupid) -- they're over-complicating the solution. Fluid directly in the chip might be a good idea, but let conduction and natural convection handle the heat transfer to the heat spreader. Don't over-complicate this thing with a pump that can break the second a nanometer particle gets into the system.
  • by imgod2u (812837) on Wednesday April 26 2006, @08:23PM (#15208953) Homepage
    I'm no expert in ASIC design but that doesn't sound like the best thing to have in your extremely sensitive high-speed signals. I assume this field will remain constant and won't provide noise for the chip (or at least I hope) but it will introduce an electrical bias that needs to be planned and compensated for during the chip's layout.
  • So very appropriate (Score:3, Funny)

    by Anonymous Coward on Wednesday April 26 2006, @09:05PM (#15209158)
    Not only is this literally "cool," but many geeks are used to operating a micro-pump..........

    [crickets...]
  • Pointless for desktop PCs (Score:3, Interesting)

    by Rob Simpson (533360) <bertsimpson@y3.1415926ahoo.com minus pi> on Thursday April 27 2006, @12:37AM (#15210050)
    "Innovative cooling systems will be needed for future computer chips that will generate more heat than current technology"

    Except for supercomputers, servers, and hard-core gamers with air conditioning, who is going to want chips that will generate substantially more heat than current chips? If CPUs alone start using hundreds of watts of power, people are going to take notice, and even the most naive shopper will start taking this into account. Already, Intel has realized [wikipedia.org] that their ridiculous space heaters are a dead end.