ARM Offers First Clockless Processor Core

Sam Haine '95 writes "EETimes is reporting that ARM Holdings have developed an asynchronous processor based on the ARM9 core. The ARM996HS is thought to be the world's first commercial clockless processor. ARM announced they were developing the processor back in October 2004, along with an unnamed lead customer, which it appears could be Philips. The processor is especially suitable for automotive, medical and deeply embedded control applications. Although reduced power consumption, due to the lack of clock circuitry, is one benefit the clockless design also produces a low electromagnetic signature because of the diffuse nature of digital transitions within the chip. Because clockless processors consume zero dynamic power when there is no activity, they can significantly extend battery life compared with clocked equivalents."

Soooo...

[Morkano (786068)]

Soooo... How many mHz does it run at?

Re:Soooo...

[coren2000 (788204)]

I tried to figure it out, but I got a divide by 0 error.

Re:Soooo...

[neverkevin (601884)]

"1. Equivalent MHz is the speed in MHz needed by an ARM968E-S to achieve equivalent performance"

Re:They come in; fast, faster, fastest and OMGspee

[Spy der Mann (805235)]

They come in 4 models: fast faster fastest OMGspeed

I thought they came in Light Speed, Ridiculous Speed and LUDICROUS SPEED!

Synchronisation?

[Poromenos1 (830658)]

Can a processor like this do things like play sounds? If it doesn't have a clock I don't think it could measure time accurately so it could reproduce the samples. What other drawbacks are there?

Re:Synchronisation?

[EmbeddedJanitor (597831)]

The peripherals (serial ports, sound, LCD,...) are still clocked. The core is synchronised with peripherals by peripheral bus interlocks.

This is not really any different than the way a clocked core synchronises with peripherals. These days devices like the PXA255 etc used in PDAs run independent clocks for the peripherals and the CPU. This allows for things like speed stepping to save power etc.

Horrible summary

[Raul654 (453029)]

I read the summary and cringed. (1) Don't call them clockless -- they're called a-synchronous, because (unlike a synchronus processor, one with a clock), all the parts of the processor aren't constantly starting and stopping at the same time. A typical synchronus processor can only run at a maximum frequency inversely proportional to the longest length in the critical path - so if it takes up to 5 nanoseconds for information to propagate from one part of the chip to the other, the clock cannot tick any faster than once every 5 nanoseconds. (2) One very serious problem in modern processors is clock skew [wikipedia.org] - if you have one central clock, the parts closest to the clock get the 'tick' signal faster than the parts farhther away, so the processor doesn't run perfectly synchronously.

VAX 8600

[Tjp($)pjT (266360)]

Maybe the first commercial micro-processor. DECs VAX-8600 [microsoft.com] was asynchronous. And it smoked for the day. I worked on some of the multi-variant multi-source clock skew calculations for the simulator used to model the processor, among other duties. Very slick hardware for the time. External syncronous contexts are maintained of course for syncronous busses but the internal processor speed is quicker in theory and cheaper power since you have fewer switching transitions. Think of the fun in ECL logic back then. :)

Re:Horrible summary

[Peter_Pork (627313)]

Too late, they ARE called clockless CPUs:
    http://en.wikipedia.org/wiki/CPU_design#Clockless_ CPUs [wikipedia.org]
Yes, they are based on asynchronous digital logic, but calling them clockless is ok. They do NOT have a clock signal.

One of the top problems in CPU design is distributing the signal to every gate. It is very wasteful. Clockless CPUs are a revolution waiting to happen. And it will. The idea is just better in every respect. It will take effort to reengineer design tools and retrain designers, but they are far superior (now that we really know how to make them, which is a recent development).

Asyncrhonous == Clockless

[Mateorabi (108522)]

Processors like this do not have a clock. Each piece of the processor is self-timing, with handshaking done between components to pass the data (compare this with clocked processors, where you can assume the data is at your input and valid just by counting cycles.) Asynchronous processors don't have global 'cycles' when all components must pass data.

But your assertion about critical path is slightly off. Asynch processors still have a critical path. If you immagine the components as a bucket-bregade and the data the buckets, then they may not all be heaving the buckets at exactly the same time anymore, but they will still be slowed down by the slowest man in the line. The difference is that critical path is now dynamic. You don't have to time everything to the static, worst-case component on your chip. If you consistenly don't use the slowest components (say, the multiply unit), then you will get a faster IPT (instruction per time) on average.

And yes, you don't have clock skew any more which is nice, but you now have to handshake data back-and-forth across the chip. Of course putting decoupling circuitry in can help.

I worked for ARM...

[Toby The Economist (811138)]

I worked for ARM for four years.

Truely wonderful and very special company for the first two of those years, then it slowly and surely went downhill - these days, it's just another company. ARM's culture didn't manage to survive its rapid growth in those few years from less than two hundred to more than seven hundred.

ARM?

[aapold (753705)]

Those were the guys that fought the CORE, right?

The summary

[suv4x4 (956391)]

So in short, your next smart clock may as well have a CPU without a clock.
Those damn young'uns and their newfangled clockless clocks.

Not That Difficult

[Mateorabi (108522)]

I took an undergrad class on asynchronous chip design back in 2000. The class project was to implement the ARM7 instruction set (well, most of it) in about 5 weeks. We split it up into teams doing the Fetch, Decode, Reg file, ALU, etc. The nice thing about asynch is that as long as you have well defined, four phase handshaking between blocks you don't have to wory about global timing (there is no global "time" reference!). We were able to get it mostly done in those 5 weeks. Nothing manufacturable, and not tuned for performance, but we could simulate execution.

One of the neatest things about asynch processors is their ability to run in a large range of voltages. You don't have to worry that lowering the voltage will make you miss gate setup timing since the thing just slows down. Increasing voltage increases rise time/propegation and speeds the thing up. The grad students had a great demo where they powered one of their CPUs using a potato with some nails in it (like from elementary school science class.) They called it the 'potato chip'.

Re:Not That Difficult

[Manchot (847225)]

Another cool thing about asynchronous processors is that you can see the effect of temperature on the processor's speed. Wikipedia [wikipedia.org] describes a demonstration in which hot coffee placed on the processor caused it to visibly slow down, while liquid nitrogen caused its speed to shoot up.

So, no more System clock in the corner of my OS?

[ollj (966671)]

"What time is it?" "Shut! The! Fuck! Up! I'm saving energy here!"

Computer Science has lost it's history somewhere..

[hlh_nospam (178327)]

This is certainly not the first commerical processor without a clock. The PDP/8 operated using a series of delay lines arranged in a loop so that the end of an instruction triggered the next one. One of the EE courses I took (back when EE majors still had to use real test equipment and soldering irons) involved a design of a clocked version of a PDP/8 as a class project.

Gads. Now that I'm "overqualified" to write software (i.e., employers don't seem to think experience is worth paying any extra for), the geek world has completely forgotten that it even has a history.

Clockless chip overview

[Charan (563851)]

This seems to be a good overview of clockless chips. I can't vouch for its accuracy (not my area), but the source - IEEE Computer Magazine - should be good. The article was published March 2005.

(warning: PDF)
http://csdl2.computer.org/comp/mags/co/2005/03/r30 18.pdf [computer.org]

Transmeta's Crusoe was supposed to be clockless

[Vexar (664860)]

For those of us with short-term memories, we can go back in time and read historical articles about the Transmeta Crusoe [slashdot.org] processor, which was supposed to be clockless. Of course if you go to their Crusoe Page [transmeta.com] today, their pretty diagram sure has a clock.

What did I miss? I remember the hype, the early diagrams of how it was all supposed to weave through without the need for a clock. Would someone care to elaborate on the post-mortem of what was supposed to be the first clockless processor, 4 years ago?

Sweet!

[ixtapa (903468)]

I can't wait to get my hands on one of these and over-asynch the hell out of it. Imagine running it under dry ice - I bet it could run up to 50% more clockless over its default clocklessnes.

Why is async good

[quo_vadis (889902)]

I know typing this out will be useless, and it will get overlooked by the mods, but I might as well say this. Asynchronous designs have several advantages :

1. It will give good power consumption characteristics i.e. low power consumed, not just because of the built in power down mode, but also because of the voltage the chips will be running at. By pulling the voltage lower than a synchronous equivalent, it will be simpler to have greater power savings. This becomes possible if you are willing to sacrifice speed. and in async devices, speed of switching can be dynamically altered as each block will wait till the previous one is done, not until some outside clock has ticked.

2. Security: Async designs give security against side channel power analysis attacks. As all gates must switch (standard async design usually uses a dual rail design, so most gates means all gates along both +ve & -ve switch), differential power attacks become much harder. Thus async designs are perfect for crypto chips (hardware AES anyone?)

3. elegance of solution:the world is generally async. Key presses are, memory accesses are. so why not the processor :). (Yes I know busses are clocked, before you start, but if they were not.... )

But they have several points of disadvantage:

1. They are hard to do. Especially using the synchronous design flow that most of the world uses. Synchronous tools assume, especially in RTL, that the world is combinational, and that sequential bits are simply registers that occur once a clock cycle (not true for full custom designs like intel and amd, but for slightly lower level : esp ASIC design)

2. The tools that exist now, are either able to do good implementation using only a few gates ie small functions or bad implementations, that are in worst case as slow as synchronous equivalents but are larger functions. Tools exist like http://www.lsi.upc.edu/~jordicf/petrify/ [upc.edu] Petrify , but these become unusable for circuits with more than ~50 gates.

3. Async designs are usually large. This is not always true, but standard async designs are usually implemented as dual rail or using 1-of-M encoding on the wires. But the main overhead comes from the handshaking circuitry. For really fine grain pipeling, the output of each stage must be acknowledged to the previous stage. This adds a massive overhead, as it necessitates the use of a device called the Muller C Element, that sets the output to the output, only if the inputs are the same, or retains the previous value, if not. Many copies of this element are usually required, and its this that adds space, for example, a simple 1 bit OR gate, that would usually have 4 transistors, has 16 transistors for the dual rail async implementation.

For the time being, I think they will find a lot of use in low power applications - such as embedded microcontrollers/processors, in things like wireless sesnor networks, and security processors. However I believe that full processor design is very far off.

Re:That's odd

[temojen (678985)]

Many current CPUs don't have built in clocks, but still need them. This architecture is very different. It doesn't need a clock at all. All the timing is based on the propagation delay through the gates. This is extremely difficult to do right.

Re:That's odd

[orangesquid (79734)]

Async work is very annoying when the whole system is one state machine.

Hence, large-scale async work is often based on every data transfer between modules being sent along with a PULSE or READY signal. Of course, every module has to be designed so that its output is ready when it propagates the pulse... otherwise there's bogus output into the next module. Basically, one module having the propagation delay timed incorrectly can kill the whole system. BUT, with fast logic, your system will simply run as fast as the hardware can handle...

Commercial async processors have been around for AGES [multicians.org] -- but modern logic IC-based processors are rarely build and sold on a large scale, being mostly experimental designs.

Re:The next palm pilot?

[OrangeTide (124937)]

It theoretically should make a good chip for PDAs and cellphones. I think initially it will be used as a controller for automobiles though. Asynchronous chips are currently not that fast because the tools used to design them are incredibly new, but they are already very low power. I predict we'll have them all over the place in a couple years is all. Intel and AMD might already be considering (or may already have) used asynchronous logic in parts of their processors or support chipsets.

Basically a good asynchronous chip would draw almost no power while it's waiting for something (like I/O events from network, keyboard, timers, etc). And it would instantly ramp up and handle the event as fast as it possible could. The speed is generally a factor of voltage and temprature. It's how fast the gates can switch and perform interlocks under current conditions, rather than what rate a clock is driving everything.

It's going to be interesting to see what performance metric is used on these "clockless" chips by the industry and by the marketing/sales types. MIPS? FLOPS? SPECmark? not that MHz was ever a good benchmark, but things like MIPS is a lot easier to manipulate to make your product appear faster than your competitors.

Re:How fast is it?

[tomstdenis (446163)]

ARM doesn't typically target super fast designs. They go more for low power and then reach for efficiency.

So this core wouldn't be designed for speed.

Also for many embedded platforms the cpu speed is less important compared to power consumption and bus contention.

Tom