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Researchers Design Microchip Ten Times More Efficient

Posted by ScuttleMonkey on Mon Mar 17, 2008 02:11 PM
from the proof-of-concept dept.
WirePosted writes to mention that a new highly efficient microchip has been announced by researchers from MIT and Texas Instruments. The new chip touts up to 10 times more energy efficiency than current generation chips. "One key to the new chip design, Chandrakasan says, was to build a high-efficiency DC-to-DC converter--which reduces the voltage to the lower level--right on the same chip, reducing the number of separate components. The redesigned memory and logic, along with the DC-to-DC converter, are all integrated to realize a complete system-on-a-chip solution."
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  • by Naughty Bob (1004174) on Monday March 17 2008, @02:17PM (#22776304)
    The article doesn't say whether these chips are cheaper to make than the current technology. That will be the deciding factor regarding how soon these make their way into our portable devices.
    • by pilgrim23 (716938) on Monday March 17 2008, @02:22PM (#22776362)
      well whatever the outcome, the Moore the merrier. Thats the law.
    • by Shikaku (1129753) on Monday March 17 2008, @02:25PM (#22776410)
      The processors, chances are, are not very useful for things that require more processor horsepower. The article mentions use in things that could be powered by minuscule power input (i.e, body heat). I think it was invented for that purpose, that the power bill will be minuscule at worst, nonexistent at best for these things. Therefore, use in portable devices for now are not so much, except maybe a simple PDA that requires no batteries, only heat.
      • Some of us have a better coefficient for heat transfer. (Am I saying that right? Some of us "put off" more of our body heat than others.)

        Like for instance. If I touch the girls here at work (...I'll likely lose my job *rim shot* [you know someone was thinking it]), they are usually "colder" than my body temp. Would this mean that the "warmer feeling" bodies would power these easier? Would those with "cold bodies" not have enough heat to power their PDA at all? Does it matter?
      • Re: (Score:2, Interesting)

        The thing about this is body heat is not a source of power. To have a source of power (for a thermocouple to work) you need a temperature differential, so you would need a part of the thermocouple sticking out of your body. Another thing is no matter how low the current drawn from batteries is they still need changing batteries only have a limited shelf life (with no current drawn.) Lower power means smaller batteries but I dont think thermocouples are a viable source of power for implants, perhaps they c
      • Processors are not engines, there is no horsepower. Electrons don't drive faster with more heat, they're running less efficiently.
        • Re: (Score:3, Informative)

          gaahh!!
          (preview is my friend, preview is my friend, preview is my friend . . . )
          Power is power, electrical or horse.
          Intel core 2 duo => approx 35 watts = 0.047 HP,+/-
    • Re: (Score:3, Informative)

      Not really.... Design is usually more expensive than production. Production cost is pretty much insignificant. (Except memory)
    • Any examples where combining functions into a single (electronics) module hasn't paid off?
    • The article doesn't say whether these chips are cheaper to make than the current technology.

      And the cost to implement will also include patent licensing for chip manufacturers, not just the production costs as it may for current designs.
  • Dup? (Score:5, Informative)

    by Bob-taro (996889) on Monday March 17 2008, @02:21PM (#22776342)

    I thought this sounded familiar. [slashdot.org]

  • by damn_registrars (1103043) on Monday March 17 2008, @02:21PM (#22776348) Journal
    The first thing that came to mind when I saw this article was the Transmeta [wikipedia.org] Crusoe [wikipedia.org] processor. Which unfortunately never achieved much of any significant market penetration. Indeed, it seems that you really have to have something more than just an incredibly efficient chip in order to compete against the Intel - AMD behemoth.

    Personally, I would love to see a chip that requires very low power make it into the mainstream market. I think it would great to have something like that for the miniITX form factor or something of that nature that hobbyists could tinker with and find fun applications for. The Transmeta, unfortunately, never realized that as far as I ever saw.
    • by ejtttje (673126) on Monday March 17 2008, @02:29PM (#22776444) Homepage
      I don't think they're demonstrating a particular CPU, but a technology or design strategy that can be built into *any* chip. So Intel or AMD could pick up this research with their own chips. (subject to patents and licensing of course)

      Also, from the article: "So far the new chip is at the proof of concept stage. Commercial applications could become available "in five years, maybe even sooner, in a number of exciting areas," Chandrakasan says
      • Re: (Score:3, Informative)

        Sense the research was sponsored by TI, I am sure this technology will find its way into all sorts of embedded devices. Think everything from 32-bit uCs to Opamps. If it really does increase power efficency 10 fold, it wouldn't supprise me to see AMD and/or Intel license the technology from them for high speed uPs.
    • The reason is that they needed to build up an industry to accept them. There were already other chips fabs that had a name. So what did transmeta do? Nothing. They should have spent a few bucks and looked for new ideas that used their chip. They only needed a few interesting ideas to make it. How much money? What a million / idea? Even had it cost them 3 million, then it would have been NOTHING in the long (or even short) run.
    • Well, if you read the fine article you will see that the applications they talk about are things like medical implants, where you'd like to avoid surgery every few years to replace the batteries. The article makes no claims that these chips will appear any time soon in your desktop computer. Since they save power in the usual way (by reducing voltage) they're probably slower than stock chips. This doesn't matter in a lot of imbedded applications but it won't attract the gamer crowd.
      • by damn_registrars (1103043) on Monday March 17 2008, @03:06PM (#22776802) Journal

        Since they save power in the usual way (by reducing voltage) they're probably slower than stock chips.

        Yes, I do recall that the Transmeta chips were a fair amount slower than the Intel / AMD chips that were out at the same time, though in some regards one could say they made up for it with far better battery life in laptops.

        This doesn't matter in a lot of imbedded applications but it won't attract the gamer crowd.

        I can't speak for everyone, but I wasn't planning to run duke nukem forever on a low-power system... But I can think of plenty of typical household applications that would be well suited to a cpu that consumes less power.
        • Additionally, when you make the voltage smaller, you can increase the complexity of the silicon, packing more functions per unit volume.
    • by PPH (736903) on Monday March 17 2008, @02:52PM (#22776654)

      That depends on youe definition of 'the mainstream market'. This technology may never appear in desktop/laptop PCs, but become popular in handheld devices where power consumption is a major issue. There is a limited amount of power saving economically feasible in PCs as long as the displays and other peripherals continue to be major power hogs.

      Another interesting market might be in server farms. But I wouldn't count on this driving the market. CPU architectures specific to servers haven't sold well, so this isn't an economically viable niche.

      Microcontrollers are a large enough market segment to justify the R&D. I forget where I read this, but if you take the total percentage of the uP and uCs installed in PCs and round it to the nearest whole percent, that number is zero.

    • by Phat_Tony (661117) on Monday March 17 2008, @02:53PM (#22776664) Homepage
      Transmetta had radically better power consumption for a while and might have some day come to dominate the portables market, had they retained an advantage like the one they had at their debut. Transemetta's problem was underestimating how rapidly Intel could improve the power efficiency of their chips. In response to Transmetta, Intel suddenly got serious about power consumption and got competitive so fast it left Transmetta with little to differentiate their chips from the competition.

      Like anything, the commercial viability of this doesn't just depend on how much better it is than what's already out there, but on how long it'll take their competitors to catch up.

      Transmetta didn't do so well, but the real winner of Transmetta's actions was the consumer. Transmetta drove Intel and AMD to improve efficiency much more rapidly than they had been. Let's hope this new technology makes it into production and does the same.
  • Cutting to the chase (Score:5, Informative)

    by objekt (232270) on Monday March 17 2008, @02:22PM (#22776352) Homepage
    Just like all these articles on breakthroughs in energy efficient technology, there's only one thing I'm interested in.

    from TFA:

    So far the new chip is at the proof of concept stage. Commercial applications could become available "in five years, maybe even sooner, in a number of exciting areas," Chandrakasan says.
    • Re: (Score:3, Insightful)

      So as usual, something ten times better than we have now is going to be available in five years. Since these breakthroughs happen all the time, we continue our remarkably linear trend by continually filling in the gaps.
      • So as usual, something ten times better than we have now is going to be available in five years.

        Sure, in five years the available chips will be a lot better than the stuff that's here now. But when this technique has matured enough, it could be applied to the chips in 5 years and we'll still get a 10 fold improvement! (Or something like that :-P)

        This seems to be a complete other kind of advancement than regular chip evolution we've seen so far.

        • by Jerry Coffin (824726) on Monday March 17 2008, @03:22PM (#22776968)

          This seems to be a complete other kind of advancement than regular chip evolution we've seen so far.


          There's not enough in TFA to say for sure, but I'd guess rather the opposite. The main thing they mention is a lower power supply voltage. Power supply voltages have been dropping steadily for a long time. Once upon a time, the most common logic family was the 7400 series, which all used 5 volt power supplies. Somewhat later 3.3 volt CMOS logic was introduced. Most CPUs, memory, etc., now use somewhere between 1 and 2 volts.

          For the most part, you get a trade-off between voltage and speed -- with a higher voltage, you can charge up a more reactive load more quickly, giving faster rise and fall times. That translates directly to higher bus speed.

          At the same time, the power you use is the product of the voltage and the current, so as you raise the voltage you raise the power usage. Worse, the current you drive through a given impedance also rises linearly with the voltage -- so the power usage is proportional to the square of the voltage.

          That (probably) explains to a large degree how/why they've reduced the power usage by a ration of 10:1 by reducing the voltage by a ratio of something like 4:1 (in theory, a 10:1 power reduction should imply a voltage reduction by the square root of 10, roughly 3.16).

          In any case, however, nothing in the article really suggests that they've departed a great deal from the path everybody's been following for quite a while. Of course, they may have done something truly radical here -- but based on what they've said, that isn't necessarily the case.
          • They seem to have departed from standard practice in two ways. First, they use an on-chip DC-DC converter to dynamically scale the voltage down to the minimum required to meet whatever performance metric is specified. Second, they intend to power it using some kind of energy-harvesting technique (namely human body heat). I agree the reduction of power is just first-order physics, but how they do it is quite interesting.
    • Commercial applications could become available "in five years, maybe even sooner, in a number of exciting areas," Chandrakasan says.
      I was about to post something witty about these guys having to run and hide from the Moore's Police...

      And then I read that quote. Yep... just another aspirational "news" story. Tag under: "flyingcars", "dukenukemforever" and "robotbulter".
  • by Terje Mathisen (128806) on Monday March 17 2008, @02:41PM (#22776560)
    As the MIT report states, the key was to make the chip operate at 0.3 V instead of ca 1.0V

    Since power usage is (roughly!) proportional to voltage squared, getting the chip to run at less than one third the usual voltage will indeed give an order of magnitude reduction in power usage.

    From the report:

    One of the biggest problems the team had to overcome was the variability that occurs in typical chip manufacturing. At lower voltage levels, variations and imperfections in the silicon chip become more problematic. "Designing the chip to minimize its vulnerability to such variations is a big part of our strategy," Chandrakasan says.
    I.e. current state of the art transistors does not work reliably at such voltage levels, I'm guessing that they have to give up significant parts of the theoretical power reduction in order to make it work at all.

    Terje
    • Without RTF I would guess that you could run every voltage as needed on a CPU instead of a single voltage. The MMX processor would need a higher voltage than the pipeline units (just making an example for illustration)

      Perhaps memory chips may hold data at a much lower voltage and only need a boost during a write operation.
    • So it sounds like "10 times the efficiency" means 1/10 the power. I read the article specifically to see how they defined a tenfold increase in efficiency. I imagined that an increase from, say, 9% to 90% was not reasonable to expect. Maybe it was energy converted to waste heat that was reduced.

      Anyway, I didn't find an explanation in the article. So what is a theoretical 100% efficiency with respect to logic circuits? Every electron turned into a bit of information? Every pair of electrons? It seems

  • If memory serves power dissipation has a formula on the order of I2R, I being current in amps and R being resistance in ohms. So, if you had a chip that ran on 1,000 volts at 30ma instead of the usual 1 volt and ~30 amps wouldn't it be just as efficient as a 0.3volt chip running at (and I'm guessing here because tfa doesn't mention current) 1 amp or maybe even less?
    • I believe current is constant in this case, so that the power decreases with the square of V. By reducing the voltage to 1/3.3 the typcial usage, a theoretical power decrease to (1/3.3)^2 or 1/10 is achieved. Again , in theory, and provided that they can get the transistors to work at that voltage. Then again, IANAEE, so I wouldn't take that as genuine truth.
    • Re: (Score:3, Interesting)

      You're thinking about a physics-land purely resistive circuit, where we can arbitrarily control the resistance. Unfortunately, that's not quite the case with very-much-minified microprocessors. We can't arbitrarily force a couple hundred million transistors to use less current. And at the same time, transistors can be designed so that they don't require 1000V to operate.

      Every transistor leaks current to some extent. And as those transistors get smaller, that amount of leakage likes to get bigger, becau
    • Re: (Score:2, Interesting)

      You're assuming R is independent of applied voltage, which is not true for any transistor. Resistance is a derived quantity that can be (for example) formulated in terms of the ratio of resulting current from an applied voltage. Ultimately, electronic devices require a certain current to operate, so it's not as simple as minimizing power by arbitrarily scaling down current. If you cannot supply enough current to a system, transistors may not have enough juice to produce those 1's and 0's quickly enough,
  • by quo_vadis (889902) on Monday March 17 2008, @03:21PM (#22776962) Journal
    Their work is definitely interesting, but I think some important questions remain unanswered, the main among them is the tradeoff between correctness of operation vs. performance because of variability. There is a paper in ISLPD 2006 which shows that for a 65nm circuit to operate at 0.3 V, the clock period must be scaled up by a factor of at least 230% to compensate for variability related issues. Additionally, there is a huge problem as far as tool support goes. This is not just mix-and-match style design. In order for this to have widespread use, it needs to work well in the EDA tool workflow. This means that libraries (and to some extent transistors) need to be characterized well at the subthreshold operating voltages. This causes a catch-22 situation. In order to design something using this subthreshold voltage technology, you need good transistor models, but the fabs have no interest in providing these models unless there is large customer demand. It is pretty expensive to get good models. The way this works is most fabs actually create transistors/gates at the given feature size, characterize them, including parameters for variation/process variability and give these to their customers, who design their chips based on these simulations. The reason these are so important is that for synchronous circuits, you have to base the design of the clock scheme on the worst/average case delay, and this you can get only by doing complete (usually Monte Carlo based) simulation of the chip using the transistor models that fab gives you. If you base the parameters solely on simulation based tools, you ignore all sorts of effects in the real world, causing a massive drop in yield(i.e. working chips made by fab).
  • Slightly O.T., but can I petition for a reusable "seeyouinfiveyears" tag that gets tacked onto any article where the technology will be out of the lab and in the factory in 'five years'?

    Because 5 years from now, I'd really love to quickly and easily see just how accurate or inaccurate that industry standard five-year prediction really is.
  • by jcr (53032) <jcr@mac.cUMLAUTom minus punct> on Monday March 17 2008, @04:37PM (#22777692) Journal
    If they have a substantially better DC-DC conversion technology, that's worth a lot of money to a lot of people already.

    -jcr
    • by Bob-taro (996889) on Monday March 17 2008, @02:49PM (#22776624)

      It seems like all of American know-how goes into designing things like this, then companies move the jobs overseas ...

      The researchers are: "graduate students Yogesh Ramadass, Naveen Verma, and Joyce Kwong, along with Professor Anantha Chandrakasan". While they may very well all be U.S. citizens, it makes me want to ask for a precise definition of "American know-how".

      • I take it you haven't been inside an engineering college lately.
        • by Bob-taro (996889) on Monday March 17 2008, @03:31PM (#22777072)

          I take it you haven't been inside an engineering college lately.

          Even when I was in engineering school, the majority of graduate students were foreign. I forget where, but I once read a quote that went something like this: "American universities are the best in the world. In fact, they are so good that American high school graduates can't compete in them".

      • Re: (Score:2, Insightful)

        The know how to get them all into one institution doing work for one of our companies at one of our schools has to count for something.
      • Who paid for it? Who exactly is Anantha Chandrakasan? Trained at Berkley and MIT. All the current work took place at MIT in association with a DARPA grant. Yeah, I would say that is America know-how as well as funding.
      • by gnick (1211984) on Monday March 17 2008, @03:31PM (#22777076) Homepage

        The researchers are: "graduate students Yogesh Ramadass, Naveen Verma, and Joyce Kwong, along with Professor Anantha Chandrakasan". While they may very well all be U.S. citizens, it makes me want to ask for a precise definition of "American know-how".
        You were expecting to see "graduate students Geronimo, Running Bear, and Pocahontas, along with Professor Hithawea"?
    • I have actually wondered if an implanted version of a bluetooth headset would be possible if one could provide power from the heat transfer of the head.

      Tap the skin behind your ear, turns the unit on for talking. a thin hollow cable to the front of the ear for listening, and a jawbone transducer for talking.

      It would look a lot better than existing headsets(since everything is subdermal/cranial) but you would look even crazier talking in public without anything on your head. Also it couldn't be stolen or t
      • I imagine you're joking... but a Bluetooth transceiver requires far more power than could be harvested from heat transfer of the head. Sorry.