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Sun Moves Into Commodity Silicon

Posted by kdawson on Tue Aug 07, 2007 05:07 PM
from the whole-lotta-threads dept.
Samrobb writes "According to Sun Microsystems CEO Jonathan Schwartz, Sun has decided to release its UltraSPARC T2 processor under the GPL. Schwartz writes, 'We're announcing the fastest microprocessor we've ever shipped this week — delivering 89.6 Ghz of parallel computing power on a single chip — running standard Java applications and open source OS's. Simultaneously, we've said we're entering the commodity marketplace, and opening the chip up to our competition... To add fuel to the fire, the blueprints for our UltraSPARC T2... the core design files and test suites, will be available to the open source community, via its most popular license: the GPL.'" Sun is still working on getting these released; early materials are up on OpenSPARC.net.
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  • Sweet (Score:4, Funny)

    by Anonymous Coward on Tuesday August 07 2007, @05:11PM (#20148621)
    Finally a chip that you can run Java on.
    • Re:Sweet (Score:5, Informative)

      by AKAImBatman (238306) <akaimbatman.gmail@com> on Tuesday August 07 2007, @05:17PM (#20148727) Homepage Journal

      Finally a chip that you can run Java on.

      Because MAJC [wikipedia.org], picoJava [wikipedia.org], aJile [ajile.com], and Jazelle [wikipedia.org] don't count, right?
        • Re:Sweet (Score:4, Insightful)

          by heinousjay (683506) on Tuesday August 07 2007, @07:39PM (#20150463) Journal
          It's called a joke. You may hear a few of these on this "slashdot" website

          The important thing to note is that the "jokes" often lack humor, so recognizing them becomes a terrifying ordeal of memorizing the groupthink prejudices.
        • Re: (Score:3, Interesting)

          I wouldn't say that. On proper hardware, it's fast enough.

          What I would point out is that x86 processors are incredibly crude, crufty and rather antiquated, retaining, even in the 64 bit implementations, features that were used in the lowly 8088/8086. In fact there was a time a selling point of the processors was that 8080/8085 assembly code assembled and ran correctly on 16-bit hardware. I would not be surprised if lots of CP/M software did have their first PC-DOS versions by little more than a straight rec
    • Re:Sweet (Score:4, Funny)

      by Lindsay Lohan (847467) on Tuesday August 07 2007, @05:22PM (#20148809) Homepage Journal

      Finally a chip that you can run Java on.
      Will these "Java chips" make me look fat?
  • by Shadowlore (10860) on Tuesday August 07 2007, @05:12PM (#20148631) Homepage Journal
    That's what I got the first time I tried loading this article on /.

    But seriously, what's the real point? Are the means to actually make one of these processors beyond 99% of companies and pretty much 99.99% of the people on the planet? What about the patenting of the process or equipment to actually make the processor?
    • Re: (Score:3, Insightful)

      it was beyond most people to own a computer in 1960

      now most people in developed countries use dozens (including embedded systems) every day, and a desktop of awesome (by 1960s standards) power can be had for a few days salary

      think big, cast aside pre-conceptions
    • FPGAs (Score:4, Insightful)

      by EmbeddedJanitor (597831) on Tuesday August 07 2007, @05:21PM (#20148789)
      You, Yes, I mean YOU! can easily build your own CPU using FPGAs.

      Many FPGA houses provide free ARM cores etc for inclusion on their FPGAs. You can build an ARM-based (or other core based) device using free download tools and run it on an FPGA that costs a few bucks. To do this the licensee need to pay a heft licencing fee to ARm or whomever. Now they can also distribute GPL cores.

      But is this really useful? To use a GPL core would mean that all the rest of the chip design would have to be released too. Very few hardware builders will be prepared to release their silicon source code because that is often the only way they have of preventing mass knock-offs etc.

        • Re:FPGAs (Score:4, Funny)

          by mrchaotica (681592) * on Tuesday August 07 2007, @10:28PM (#20151877)

          Yes, but where in Hell are you going to find an FPGA big enough/fast enough to run a full OpenSPARC implementation?

          In the bottom of Cracker Jack boxes, 20 years from now?

          • Re: (Score:3, Insightful)

            Except the Arm7 core will cost you more then 10 bucks in license fees, unlike opensparc.
            • The ARM core is free-as-in-beer if you use it on certain FPGA parts (eg. many Actel parts). The FPGA have already paid the licensing to ARM.

    • I'm thinking China. (Score:5, Interesting)

      by khasim (1285) <brandioch.conner@gmail.com> on Tuesday August 07 2007, @05:24PM (#20148847)
      Depending upon how the patents (are there patents?) are handled. China has been researching it's own chip design in the past. This could be a huge push for Sun if China abandoned trying to re-invent the wheel and just started cranking out UltraSPARC's.

      Not to mention Windows not running on such, but Linux will.

      And China would have a home source of chips for their IT industry and would not have to import Intel or AMD.
    • Various options. (Score:4, Interesting)

      by jd (1658) <imipak.yahoo@com> on Tuesday August 07 2007, @05:32PM (#20148965) Homepage Journal
      One would be to build a simulator that is accurate at the level of silicon, so that you can cross-compile and run binaries for this CPU on a non-native architecture. Another would be to look at some specific module within the core and re-use the code within an OpenCores project. A third would be to reverse this - take OpenCores code (or write your own) and generate a module that would work within the T2 and would provide functionality the developers might want. A fourth would be to produce a specialized version of the chip (rad-hardened, for example) without paying license costs. And so on.
      • Re:Various options. (Score:5, Interesting)

        by mdmkolbe (944892) on Tuesday August 07 2007, @05:49PM (#20149199)
        I do high performance numerical computation research, and something like this would help a lot.

        As part of my research I have to hand tweak and tune the inner most loops of our algorithms. Unfortunately, the performance of moderns processors behaves so counter-intuitively when pushing the floating-point units to the max, that it is basically impossible to guess whether a certain change will speed up or slow down the computation. Being able to know *exactly* what in in the CPU would greatly help with this.
        • Re:Various options. (Score:5, Interesting)

          by jd (1658) <imipak.yahoo@com> on Tuesday August 07 2007, @06:26PM (#20149693) Homepage Journal
          Generally, you have a library of routines tuned to different ranges of conditions, optimized by actually running them at different settings. ATLAS does this, for example, as do a number of other optimized libraries. However, you're absolutely right that modern cores are very sensitive to a range of conditions. Lookup/interpolation units are obviously not going to respond in a fixed interval, it will depend on what point you hit. Does the FPU have enough internal memory to avoid swapping in and out of core during calculations? If you re-order operations, can you squeeze better performance out of the L1 and L2 caches? Is a composite instruction faster or slower than executing the individual opcodes that would produce the same result?

          I don't know of anyone who has gone to the gate level to tune software - I've never found it necessary to go beyond a high-level definition of the processor, the sizes/speeds of the caches, the lanes between the segments, the length of each pipeline segment and other such information that can be basically listed. However, such information will not reveal unintended features (distinguished from bugs by being useful) and won't expose every possible shortcut.

          HPC is fun, though I agree that modern processors are counter-intuitive. They can do some seriously weird things at times, which is why CPUburn is such an interesting program. If only the developers still maintained it. :( A CPU that can self-destruct performing legal, documented operations is a buggy CPU. That goes for any other hardware, too.

            • Re:Various options. (Score:5, Interesting)

              by jd (1658) <imipak.yahoo@com> on Tuesday August 07 2007, @11:18PM (#20152273) Homepage Journal
              "Should" and "Is" are often quite different. For example, no programmer of the 8086 would be caught dead using the instruction to roll left or right a given number of times. Nononono. It was far, far faster to have one operation for each roll. Division and multiplication on the 8087 was so slow that people even tried developing workarounds in software to get better performance! Multiplying by an integer amount was generally stupid - you were often much better off loading the value into two stack locations then adding repeatedly.

              CISC eventually collapsed precisely because of this. RISC was faster - far faster - without the composite instructions. Hybrids, like the Pentium series, have since developed, where the underlying architecture is RISC and the composite instructions are emulated by being split into much simpler ones. So far, so good, so what? You still have a translation layer. You still have that decomposition. That's not free, you know. It takes time.

              So why do this at all, and not have a pure RISC system? Well, many CPU manufacturers asked the same question. And decided to do exactly that. Have a pure RISC architecture. They generally do the same amount of real work with a fifth of the clockspeed of a CISC/RISC hybrid - so they run cooler and you can pack more into less space.

              Why don't Intel and AMD do this? Oh, they'd love to! The Itanic proved many things, though, one of which is that the 8086-style CISC layer has to remain. The customers have too much legacy software now. Not only are consumers locked into Intel's architecture, so is Intel! There's nothing they can do to escape, unless they make a chip that has some cores on the old design and some on a new one. But who is going to buy a processor that costs more and does less (for now)? Nobody. Thank you.

              This should be the lesson that companies learn from the IT industry (but won't): Too much lock-in locks the company in as well, making necessary changes and corrections impossible. Given enough time and enough failures to change, the company will destroy itself.

              • this is one of the great advantages of package management and repositories. if ubuntu wanted to change something critical about a program which would effect 20 others on the system, they can do this and offer all modified packages for download at the same time. granted, the download could become big if there was a huge change, but being open-source, they could just compile everything new for that and then offer a new install cd.

                the only things tying linux to certain architectures are flash, nvidia, ati e
              • Re:Various options. (Score:5, Interesting)

                by kestasjk (933987) on Wednesday August 08 2007, @03:18AM (#20153553) Homepage

                You still have a translation layer. You still have that decomposition. That's not free, you know. It takes time.
                It doesn't really take time, it just takes a longer pipeline and more space on the chip. Micro-ops from one instruction can get executed while instructions that are coming up get broken into micro-ops.

                The main reason this is actually slower is the ordering of instructions. Intel chips have out-of-order execution that lets them run micro-ops from instructions in a different order that will make things faster and make more use of all the parts of the processor.

                If a compiler could do this instead of the processor, by ordering the micro-ops itself, Intel wouldn't need die space for out-of-order execution. The space could be used for more cache or to squeeze more cores in.
                Also the compiler would be able to do better optimization because it has the bigger picture of what's coming up, and it has more time to do the optimization because it doesn't do it on the fly.

                They generally do the same amount of real work with a fifth of the clockspeed of a CISC/RISC hybrid - so they run cooler and you can pack more into less space.
                That's a pretty wild exaggeration. (UltraSPARC sure isn't 5x faster than Core 2 Duo, and PPC wasn't 5x faster either, despite what Apple marketing used to want you to think).
                Intel make excellent processors even if they do have to do CISC-RISC translation, and they still beat any competing RISC processor hands down (except in specialized applications like supercomputers or Sun benchmarks). This isn't because CISC is better than RISC, it's just because the difference isn't nearly as large as you make out, and Intel has a massive R&D budget that offsets any performance decrease and then some.

                If Intel really felt it was necessary to move to a new processor they would. They talked MS into using Itanium for high end apps so I'm sure they could push a transition if they wanted.
                They could include a Rosetta style software translator for old x86 binaries, and perhaps include an x86 translator on-die (like Itanium 1 did). The reason they don't is because it wouldn't give such a large boost, and would be relatively expensive, when they can get larger speed boosts for less by going for smaller processes and optimizing micro-ops.

                It wouldn't be as big a transition as you make out, and it wouldn't give as big of a performance increase as you make out. It would be better if they had gone with RISC, but not that much better.
              • Re: (Score:3, Insightful)

                While your comment on the Itanic is partially true - the real reason it failed was the VLIW premise.

                Executing multiple instructions within a single "opcode" - and then developing a compiler to pre-determine the best path was about the STUPIDEST idea I've ever heard. Just think about it... a compiler has no idea about the REAL conditions at runtime.

                A compiler can optimize a single program thread - but can't optimize for multi-threading, multi-processing, or mixed mode execution between the OS and the applic
  • Irony (Score:5, Funny)

    by Dachannien (617929) on Tuesday August 07 2007, @05:13PM (#20148645)
    Clicking the OpenSPARC.net link returned the message: "This Account Has Exceeded Its CPU Quota"
  • ...when you are talking about a market with massive investment related non-recoverable expenses & high barriers to entry, such as processor fabrication.

    Although I submit it would be really cool to just manufacture these things in my garage.
    • by Wesley Felter (138342) <wesley@felter.org> on Tuesday August 07 2007, @05:23PM (#20148837) Homepage
      Apparently Sun will sell the chips to you already manufactured if you want.
        • by howlingmadhowie (943150) on Wednesday August 08 2007, @02:52AM (#20153419)
          well, sun sells everything from workstation upwards. they tend to use their own chips, their own connectors, their own file systems and their own operating systems, all of which are now open-source and so can be freely implemented by the "competition". by open-sourcing their intellectual property (what a wonderful oxymoron), sun is doing correctly what microsoft did wrongly in china. in china, microsoft gave windows away for free. the result? market domination but a mono-culture where computing goes from a growth market to a replacement market.

          by allowing and encouraging competition and progress, sun is keeping computing a growth market for a long, long time. sun just has to have the intellectual clout to keep their head-start (i can give you the source code, but do you know what to do with it?). it's an interesting, very honest business strategy, and the free-software licenses used will keep it honest.
  • by Anonymous Coward on Tuesday August 07 2007, @05:15PM (#20148681)
    Go look at the CPU cycles per watt that the UltraSPARC T1 delivers.

    Now, figure the UltraSPARC T2 is better than that.
      • I see a 1 GHz T1 doing quite well compared to a 2.4 GHz Opteron and a 3 GHz Xeon. Things have improved on the Intel front, but the T2 should do quite well for the workloads it is designed for. Not only does it have more threads (and I think a better memory controller), but now it has one FPU per core instead of 1 per chip. That means 8x as many FPUs. That was the real weak point and now it has been addressed.

        I can't wait to see benchmarks of this chip. It is far more interesting than "the same chip for 3 years ago, now 0.3 GHz faster" or "now with one more micro-op fuser and a 2% better branch decoder."

  • Power consumption? (Score:5, Interesting)

    by Toffins (1069136) on Tuesday August 07 2007, @05:15PM (#20148691)
    I can't wait for somebody to design a new generation of desktop PCs that have lower power consumption than that of previous generations but without sacrificing performance and graphics. Anybody know how much power typical UltraSPARC based desktop PCs consume compared to Intel or AMD based desktop PCs?
    • Re: (Score:3, Interesting)

      Get a Core2Duo or one of the new low power AMDs. The just find a modern video card that is roughly the speed of a last generation card.
      If you want super high performance and super low power ... Not going to happen. They will always have the option to pump up the speed buy pumping up that watts.
      Top of the like will have high power draw.
      You have low power options that are pretty dang fast. The trade off is just up to you.
        • Re: (Score:3, Informative)

          If I remember it right they max out at 72 watt for 8 cores running 8(?) threads each.
      • Re: (Score:3, Insightful)


        You have a short little span of attention. When Intel first hit 60W with the original Pentium there was a huge outcry about its outrageous power consumption, and it hardly performed any better than a 100MHz 486, either. After a quick die shrink, the next version wasn't so bad. Now Intel sells the Core Duo at 65W as a major innovation in power management. After Intel's Prescott, it's almost impossible for anything else to look bad. But really, should a product that never deserved to be made in the first
  • Which GPL? (Score:5, Interesting)

    by junglee_iitk (651040) on Tuesday August 07 2007, @05:16PM (#20148695)
    Nothing that it matter... just interested, but does anybody know if it is released under GNU GPL 2 or 3?
    • Re: (Score:3, Informative)

      The original T1 design was released under GPLv2 a while back, and the new T2 design will be released under GPLv2 for now as well. Using GPL v2 creates an implicit patent license so while using GPLv3 would make the situation cleared GPLv2 is probably sufficient.

      And yes if you look at the map on the opensparc.net page (when they get some quota back after being slashdotted) you'll see they are getting a vast amount of interest from China, where I gather a company is already producing an OpenSPARC T1-derived ch
    • Re: (Score:3, Informative)

      It is GPLv2:

      http://opensparc-t2.sunsource.net/ [sunsource.net]

      • by Ungrounded Lightning (62228) on Tuesday August 07 2007, @05:43PM (#20149107) Journal
        Nothing that it matter... [is it] GNU GPL 2 or 3?

        It actually matters a lot because Sun probably owns a lot of patents.


        Too true.

        If I've got this right: Under GPL3 anybody with foundry access could make the chip or a derivative, with no more patent issues than Sun itself would have. But under GPL2 they might have to enter separate license agreements to actually implement it.

        = = = =

        Presuming this release does make the chip open to anybody absent further licensing, it will be interesting to see how it affects Sun's future.

        On one hand it means any company that wants to could build the chip and sell it in competition with Sun (which has borne the development costs on the SPARC series - but recouped much of them already).

        On the other hand, they have a number of advantages: Already up and fabbing, deep understanding of the chip, etc.

        Further, one big source of resistance to adoption of their chips is the concern for what happens if Sun abandons the line, stops developing it, goes belly-up, or closes up again. With a perpetual license to others to build this chip and make improvements on it, that's no longer an issue. Even if Sun went belly-up and left them with no other sources, a big enough company with a product based on this chip could even commission the fabrication of its own chips, rather than twisting in the wind for lack of supplies. So such a company can design this chip into their product line and buy it from Sun without betting their own company on a possibly weak supplier.

        Let's see Intel or AMD compete with that that. B-)
  • by Sta7ic (819090) on Tuesday August 07 2007, @05:24PM (#20148843)
    I always wanted a Tech 2 processor.

    Oh wait...
  • by mritunjai (518932) on Tuesday August 07 2007, @07:44PM (#20150499) Homepage
    Just to quell the concerns of "abandonware" and cries of "performance benchmarks"

    Linky on numbers [sun.com]

    Summary:

    * This puppy comes ahead of Power5 and top-dog (till now) Power6
    * Highest single CPU integer and floating point performance

    Oh, and it has 2 10G network interfaces on chip... and EIGHT crypto cores to keep them running full throttle too. All this with 8 core each with its own floating point unit and 8 threads.

    Oh and BTW, Ubuntu guys just booted their distro on this puppy :-)

    So yeah, it runs Linux (too)!
  • pfft (Score:4, Funny)

    by shaitand (626655) on Tuesday August 07 2007, @08:49PM (#20151071) Homepage Journal
    'We're announcing the fastest microprocessor we've ever shipped this week'

    I bet its the only chip they've shipped this week.
  • The posters here seem to be complaining that this is worthless because individuals can't make their own processor chips.

    That's not the point. Here's the point:

    1: Sun's processors are a niche market. People don't use them because they're harder to use than cheap commodity processors from Intel. Why are they harder to use? Because not enough people use them to create the kind of economic ecosystem that drives down the price of using the processors.

    2: All over Asia are chip factories that make low-end embedded devices, RAM chips, and so on. Factories that are owned by companies that don't have the cash on hand to do the R&D to design their own processors to compete with Intel.

    3: By GPL'ing their chip designs, Sun lets all those Asian factories produce chips that perform like Intels but cost even less. This gives people an extra incentive to switch away from Intel and to create the very economic ecosystem the processor needs.

    4. Next, Sun releases enhanced versions of the chip that aren't GPL'ed. Chip consumers can now choose from fast commodity processors or more expensive deluxe models - that are still code compatible.

    And Sun can repeat steps #3 and #4 as often as they like, feeding their previous generation designs to the GPL audience as their newest designs hit the market.
      • Re: (Score:3, Insightful)

        They probably WOULD be making X86 compatibles, but they'd have to build, buy, or license an appropriate design. Last time I checked, there weren't plans for a P3 or better X86 chip available at my local library.
    • How many cores does this chip have?

      8 cores, 8 threads each.
        • what's the hardware meaning of a thread?

          As another poster has pointed out: You build a core with multiple copies of the register set and replicate (or take turns on) the associated instruction-dispatching logic.

          But these multiple CPUs share a common set of arithmetic/logic execution units, along with arbitration logic. Different threads will be doing different things at any given instant, and thus using different sections of the ALU.

          The arbitration logic decides which thread gets which hunk of ALU at any
    • Re: (Score:3, Interesting)

      I work at Sun (documenting x86 systems, as it happens) and I think you're really oversimplifying our business strategy. Just because we're doing x86 doesn't mean we're abandoning SPARC. Indeed, I see a lot of work going on with SPARC-based products. You might consider this a bad idea. (For obvious reasons, I can't possibly comment.) But it's the current business plan, and as long as that's the case, SPARC is not abandonware.
    • by WebMink (258041) <slashdot&webmink,net> on Tuesday August 07 2007, @06:19PM (#20149607) Homepage

      Nobody cared.

      Well, apart from Simply RISC [srisc.com], who used the design to build a single-core chip (S1) for embedded applications.

      And Polaris Micro [polarismicro.com] in China, who are doing the same.

      And David Miller & friends, who made Linux run on it.

      And Canonical who support Ubuntu running on it [ubuntu.com].

      And the other Linux distros picking it up.

      And... Oh, sorry, you were just trolling, right?

    • by afidel (530433) on Tuesday August 07 2007, @06:23PM (#20149661)
      The T1 is NOT abandonware, in fact I would say it is one of Sun's greatest strengths. We are doing a design for a JD Edwards data warehouse and while our JDE system is on Oracle on Windows we are looking at Unix platforms as strong choices for the data warehouse. Thanks to only needing 6 total boxes for the middleware layers for 4 different environments vs 16 Windows boxes Sun is 10% cheaper and 10% lower in 3 year operating costs despite having power sucking, expensive DB servers.
    • the GPL isn't about free it's about FREEDOM -- the rights of the end user to modify the program. Will I, as an end user of a GPL processor, be able to modify the processor? This looks like yet another big company abusing the spirit, if not the letter, of the GPL.

      Yes. You, the end user, can modify the processor to the extent that is possible for the technology involved. Since a processor is physical hardware, that means the "compilation" phase for modification involves a microprocessor fab. If you don't hav

      • Re: (Score:3, Interesting)

        The T1 excels at large scale parallel integer operations. It had up to 8 cores and 32 execution units per chip. The biggest drawback was that there was one shared anemic FPU per chip so if even a relatively small amount of your workload was floating point performance took a serious dive.

        Hmm... that makes me want a dual-CPU system with one T1 and one Cell. Imagine if they were both Hypertransport-compatible...