ARM Offers First Clockless Processor Core

Sam Haine '95 writes "EETimes is reporting that ARM Holdings have developed an asynchronous processor based on the ARM9 core. The ARM996HS is thought to be the world's first commercial clockless processor. ARM announced they were developing the processor back in October 2004, along with an unnamed lead customer, which it appears could be Philips. The processor is especially suitable for automotive, medical and deeply embedded control applications. Although reduced power consumption, due to the lack of clock circuitry, is one benefit the clockless design also produces a low electromagnetic signature because of the diffuse nature of digital transitions within the chip. Because clockless processors consume zero dynamic power when there is no activity, they can significantly extend battery life compared with clocked equivalents."

Soooo...

[Morkano (786068)]

Soooo... How many mHz does it run at?

Re:Soooo...

[coren2000 (788204)]

I tried to figure it out, but I got a divide by 0 error.

Re:Soooo...

[neverkevin (601884)]

"1. Equivalent MHz is the speed in MHz needed by an ARM968E-S to achieve equivalent performance"

Re:Soooo...

[Kj0n (245572)]

Note that the parent didn't ask for MHz, but for mHz instead.

The correct answer is: 50000000000000 - 70000000000000 mHz.

Re:They come in; fast, faster, fastest and OMGspee

[Spy der Mann (805235)]

They come in 4 models: fast faster fastest OMGspeed

I thought they came in Light Speed, Ridiculous Speed and LUDICROUS SPEED!

Synchronisation?

[Poromenos1 (830658)]

Can a processor like this do things like play sounds? If it doesn't have a clock I don't think it could measure time accurately so it could reproduce the samples. What other drawbacks are there?

Re:Synchronisation?

[EmbeddedJanitor (597831)]

The peripherals (serial ports, sound, LCD,...) are still clocked. The core is synchronised with peripherals by peripheral bus interlocks.

This is not really any different than the way a clocked core synchronises with peripherals. These days devices like the PXA255 etc used in PDAs run independent clocks for the peripherals and the CPU. This allows for things like speed stepping to save power etc.

Horrible summary

[Raul654 (453029)]

I read the summary and cringed. (1) Don't call them clockless -- they're called a-synchronous, because (unlike a synchronus processor, one with a clock), all the parts of the processor aren't constantly starting and stopping at the same time. A typical synchronus processor can only run at a maximum frequency inversely proportional to the longest length in the critical path - so if it takes up to 5 nanoseconds for information to propagate from one part of the chip to the other, the clock cannot tick any faster than once every 5 nanoseconds. (2) One very serious problem in modern processors is clock skew [wikipedia.org] - if you have one central clock, the parts closest to the clock get the 'tick' signal faster than the parts farhther away, so the processor doesn't run perfectly synchronously.

VAX 8600

[Tjp($)pjT (266360)]

Maybe the first commercial micro-processor. DECs VAX-8600 [microsoft.com] was asynchronous. And it smoked for the day. I worked on some of the multi-variant multi-source clock skew calculations for the simulator used to model the processor, among other duties. Very slick hardware for the time. External syncronous contexts are maintained of course for syncronous busses but the internal processor speed is quicker in theory and cheaper power since you have fewer switching transitions. Think of the fun in ECL logic back then. :)

Re:VAX 8600

[isdnip (49656)]

He didn't say it was a microprocessor. Actually, it was a small mainframe, in terms of size, or a high-end "supermini". It simply used asynchronous design concepts, when even the other minicomputers and mainframes of the day were synchronously clocked.

The VAX 8600 was produced by a team at DEC that had a heritage doing large computers (PDP-10, DECSYSTEM-20). It was competing, internally, with a different group with a "midrange" (VAX) heritage, who produced the VAX 8800 and some other machines. There was

Re:Horrible summary

[Peter_Pork (627313)]

Too late, they ARE called clockless CPUs:
    http://en.wikipedia.org/wiki/CPU_design#Clockless_ CPUs [wikipedia.org]
Yes, they are based on asynchronous digital logic, but calling them clockless is ok. They do NOT have a clock signal.

One of the top problems in CPU design is distributing the signal to every gate. It is very wasteful. Clockless CPUs are a revolution waiting to happen. And it will. The idea is just better in every respect. It will take effort to reengineer design tools and retrain designers, but they are far superior (now that we really know how to make them, which is a recent development).

Re:Horrible summary

[Raul654 (453029)]

If memory serves, the big problem with these chips was the possiblity of 'state explosion' - as the chip got bigger, the number of possible states increased expontentially. Has this been resolved?

You are confused

[comingstorm (807999)]

I think the confusing part is that, in the terminology of conventional, "synchronous" design, "asynchronous logic" is used to mean "the combinatorial logic in a single stage". What conventional, clock-based design typically does is break the logic up into stages with clocked latches in between, thus limiting the depth of each "asynchronous" logic stage.

Unfortunately, self-clocked design (like the reported ARM uses) is also sometimes called "asynchronous" logic design; however, this is a completely different kind of thing than the "asynchronous" combinatorial logic used in clock-based design. Self-clocked design also does combinatorial logic in latched stages, but uses a self-timed asynchronous protocol to run the latches instead of a synchronous clock. Basically, the combinatorial logic figures out when it's finished, and tells both the next stage ("data's ready, latch it") and the input latch from the previous stage ("I'm done; gimme some more data").

To close the loop, each stage can wait until there's new data ready at its inputs, and space to put the output data. Thus, in absence of some bottleneck, your chip will simply run as fast as it can.

To overclock a self-timed design, you simply increase the voltage. No need to screw around with clock multipliers; as long as your oxide holds up, your traces don't migrate, and the chip doesn't melt...

Asyncrhonous == Clockless

[Mateorabi (108522)]

Processors like this do not have a clock. Each piece of the processor is self-timing, with handshaking done between components to pass the data (compare this with clocked processors, where you can assume the data is at your input and valid just by counting cycles.) Asynchronous processors don't have global 'cycles' when all components must pass data.

But your assertion about critical path is slightly off. Asynch processors still have a critical path. If you immagine the components as a bucket-bregade and the data the buckets, then they may not all be heaving the buckets at exactly the same time anymore, but they will still be slowed down by the slowest man in the line. The difference is that critical path is now dynamic. You don't have to time everything to the static, worst-case component on your chip. If you consistenly don't use the slowest components (say, the multiply unit), then you will get a faster IPT (instruction per time) on average.

And yes, you don't have clock skew any more which is nice, but you now have to handshake data back-and-forth across the chip. Of course putting decoupling circuitry in can help.

Re:Horrible summary

[NovaX (37364)]

As others pointed out, you've made mistakes.

The most glaring is that you assume that synchronous processors can only have one clock - that's incorrect. While the clock tick is of fixed length (by design), the global clock (as seen by external parties) may run at a different speed than internal clocks.

If the a path of logic takes 5ns to complete, and its clock matches exactly, then you are perfectly optimized. You are hampered not by the clock, but by the transistor's switching speed. This path will have the

Re:Horrible summary

[Raul654 (453029)]

It's not just direct - power consumption is proportional to the *cube* of the frequency (according to the research paper I just peer-reviewed). But, there are all kinds of ways to vastly reduce that, using voltage scaling, frequency scaling, and power-down-during idling technqiues.

I worked for ARM...

[Toby The Economist (811138)]

I worked for ARM for four years.

Truely wonderful and very special company for the first two of those years, then it slowly and surely went downhill - these days, it's just another company. ARM's culture didn't manage to survive its rapid growth in those few years from less than two hundred to more than seven hundred.

ARM?

[aapold (753705)]

Those were the guys that fought the CORE, right?

Re:ARM?

[Maradine (194191)]

This, of course, at the one time I don't have any mod points -- so I can mod you "+1, I'm one of the six people in here who got that."

Re:ARM?

[Nebu (566313)]

Interestingly enough, Intel's latest project is being called "CORE" [arstechnica.com]. So yes, ARM is probably going to end up fighting CORE again.

Sun was talking about clockless chips in 2001

[tjstork (137384)]

Sun exhorts people to make clockless chips [eetimes.com]

Re:only talk

[pedantic bore (740196)]

This isn't entirely accurate.

Sun has clockless chips up and running (real silicon, not sims) and they have done some interesting things, but they don't have a complete system that's ready to ship. And there are other components out there that use the clockless philosophy to do certain things, but they're not CPUs in any sense. To give credit where credit is due, as the parent post points out, ARM beat Sun out the door with a clockless CPU that is a drop-in replacement (to some degree, anyway -- not clear how much) for an existing, established architecture. But that wasn't/isn't Suns goal (although perhaps it should be...). They're pushing in new directions, not using this to reimplement current architectures.

The summary

[suv4x4 (956391)]

So in short, your next smart clock may as well have a CPU without a clock.
Those damn young'uns and their newfangled clockless clocks.

Not That Difficult

[Mateorabi (108522)]

I took an undergrad class on asynchronous chip design back in 2000. The class project was to implement the ARM7 instruction set (well, most of it) in about 5 weeks. We split it up into teams doing the Fetch, Decode, Reg file, ALU, etc. The nice thing about asynch is that as long as you have well defined, four phase handshaking between blocks you don't have to wory about global timing (there is no global "time" reference!). We were able to get it mostly done in those 5 weeks. Nothing manufacturable, and not tuned for performance, but we could simulate execution.

One of the neatest things about asynch processors is their ability to run in a large range of voltages. You don't have to worry that lowering the voltage will make you miss gate setup timing since the thing just slows down. Increasing voltage increases rise time/propegation and speeds the thing up. The grad students had a great demo where they powered one of their CPUs using a potato with some nails in it (like from elementary school science class.) They called it the 'potato chip'.

Re:Not That Difficult

[Manchot (847225)]

Another cool thing about asynchronous processors is that you can see the effect of temperature on the processor's speed. Wikipedia [wikipedia.org] describes a demonstration in which hot coffee placed on the processor caused it to visibly slow down, while liquid nitrogen caused its speed to shoot up.

So, no more System clock in the corner of my OS?

[ollj (966671)]

"What time is it?" "Shut! The! Fuck! Up! I'm saving energy here!"

Computer Science has lost it's history somewhere..

[hlh_nospam (178327)]

This is certainly not the first commerical processor without a clock. The PDP/8 operated using a series of delay lines arranged in a loop so that the end of an instruction triggered the next one. One of the EE courses I took (back when EE majors still had to use real test equipment and soldering irons) involved a design of a clocked version of a PDP/8 as a class project.

Gads. Now that I'm "overqualified" to write software (i.e., employers don't seem to think experience is worth paying any extra for), the geek world has completely forgotten that it even has a history.

How fast is it?

[MOBE2001 (263700)]

Not to belittle the energy savings, but how fast is it compared to a clocked CPU with a similar instruction set? To me, speed the most interesting quality of a new chip design other than reliability. The problem with a clock is that clock speed is dictated by the slowest instruction. Since a clockless CPU does not have to wait for a clock signal to begin processing the next instruction in a sequence, it should be significantly faster than a conventional CPU. Why is this not being touted as the most important feature of this processor?

Re:How fast is it?

[tomstdenis (446163)]

ARM doesn't typically target super fast designs. They go more for low power and then reach for efficiency.

So this core wouldn't be designed for speed.

Also for many embedded platforms the cpu speed is less important compared to power consumption and bus contention.

Tom

Clockless chip overview

[Charan (563851)]

This seems to be a good overview of clockless chips. I can't vouch for its accuracy (not my area), but the source - IEEE Computer Magazine - should be good. The article was published March 2005.

(warning: PDF)
http://csdl2.computer.org/comp/mags/co/2005/03/r30 18.pdf [computer.org]

Transmeta's Crusoe was supposed to be clockless

[Vexar (664860)]

For those of us with short-term memories, we can go back in time and read historical articles about the Transmeta Crusoe [slashdot.org] processor, which was supposed to be clockless. Of course if you go to their Crusoe Page [transmeta.com] today, their pretty diagram sure has a clock.

What did I miss? I remember the hype, the early diagrams of how it was all supposed to weave through without the need for a clock. Would someone care to elaborate on the post-mortem of what was supposed to be the first clockless processor, 4 years ago?

Sweet!

[ixtapa (903468)]

I can't wait to get my hands on one of these and over-asynch the hell out of it. Imagine running it under dry ice - I bet it could run up to 50% more clockless over its default clocklessnes.

Why is async good

[quo_vadis (889902)]

I know typing this out will be useless, and it will get overlooked by the mods, but I might as well say this. Asynchronous designs have several advantages :

1. It will give good power consumption characteristics i.e. low power consumed, not just because of the built in power down mode, but also because of the voltage the chips will be running at. By pulling the voltage lower than a synchronous equivalent, it will be simpler to have greater power savings. This becomes possible if you are willing to sacrifice speed. and in async devices, speed of switching can be dynamically altered as each block will wait till the previous one is done, not until some outside clock has ticked.

2. Security: Async designs give security against side channel power analysis attacks. As all gates must switch (standard async design usually uses a dual rail design, so most gates means all gates along both +ve & -ve switch), differential power attacks become much harder. Thus async designs are perfect for crypto chips (hardware AES anyone?)

3. elegance of solution:the world is generally async. Key presses are, memory accesses are. so why not the processor :). (Yes I know busses are clocked, before you start, but if they were not.... )

But they have several points of disadvantage:

1. They are hard to do. Especially using the synchronous design flow that most of the world uses. Synchronous tools assume, especially in RTL, that the world is combinational, and that sequential bits are simply registers that occur once a clock cycle (not true for full custom designs like intel and amd, but for slightly lower level : esp ASIC design)

2. The tools that exist now, are either able to do good implementation using only a few gates ie small functions or bad implementations, that are in worst case as slow as synchronous equivalents but are larger functions. Tools exist like http://www.lsi.upc.edu/~jordicf/petrify/ [upc.edu] Petrify , but these become unusable for circuits with more than ~50 gates.

3. Async designs are usually large. This is not always true, but standard async designs are usually implemented as dual rail or using 1-of-M encoding on the wires. But the main overhead comes from the handshaking circuitry. For really fine grain pipeling, the output of each stage must be acknowledged to the previous stage. This adds a massive overhead, as it necessitates the use of a device called the Muller C Element, that sets the output to the output, only if the inputs are the same, or retains the previous value, if not. Many copies of this element are usually required, and its this that adds space, for example, a simple 1 bit OR gate, that would usually have 4 transistors, has 16 transistors for the dual rail async implementation.

For the time being, I think they will find a lot of use in low power applications - such as embedded microcontrollers/processors, in things like wireless sesnor networks, and security processors. However I believe that full processor design is very far off.

Re:Why is async good

[bigberk (547360)]

> Security: Async designs give security against side channel power analysis attacks

You're right about that. I research side channel attacks on crypto hardware, and my first response to this was --- well, this would make EM analysis more complicated. For those not familiar with the general approach, in side channel attacks you don't try to do anything as complicated as breaking the underlying math of the crypto. Instead you observe the hardware for emissions that can give some clues as the instructions being carried out. If your observations help give you any info about what the chip is processing, you might learn parts of keys or gain a statistical advantage in other attacks. So if it's harder to observe signals emitted (electromagnetically from the chip, then attacking the hardware is harder.

Overclocking

[Gertlex (722812)]

So I take it you can't overclock it? :D

Uhhh, this isn't ARM's first clockless offering...

[Praetor11 (512322)]

ARM made a clockless chip in 1994 for cellphones. Couldn't find an amazing reference, but a quick google turned up http://www1.cs.columbia.edu/async/misc/technologyr eview_oct_01_2001.html [columbia.edu] where they briefly mention it... The last time I heard of this stuff being used was in 2001-- I actually wrote an English paper about it purely to see if I could bore my professor :-p

Re:That's odd

[ScrewMaster (602015)]

Nope. All the pre-Mac Apple machines were based upon the MCS6502 and its derivatives. All were clocked, the original Apple ][ Standard at 1 Mhz. The Apple ///'s selling point was that it had a hardware real time clock, which was removed in later revisions because of quality issues.

Re:That's odd

[temojen (678985)]

Many current CPUs don't have built in clocks, but still need them. This architecture is very different. It doesn't need a clock at all. All the timing is based on the propagation delay through the gates. This is extremely difficult to do right.

Re:That's odd

[Manchot (847225)]

This is extremely difficult to do right.

No kidding. When I took a digital systems lab class, we had to do one simple asynchronous circuit. The corresponding state machine only had four states (compared to a computer processor, which might have a hundred states or more), but it was probably the most difficult circuit to design. Basically, you have to make sure that as you're transitioning between states, you always end up in the correct one, no matter where you may be in between.

Re:That's odd

[orangesquid (79734)]

Async work is very annoying when the whole system is one state machine.

Hence, large-scale async work is often based on every data transfer between modules being sent along with a PULSE or READY signal. Of course, every module has to be designed so that its output is ready when it propagates the pulse... otherwise there's bogus output into the next module. Basically, one module having the propagation delay timed incorrectly can kill the whole system. BUT, with fast logic, your system will simply run as fast as the hardware can handle...

Commercial async processors have been around for AGES [multicians.org] -- but modern logic IC-based processors are rarely build and sold on a large scale, being mostly experimental designs.

Re:That's odd

[tinkertim (918832)]

AHA! Found it. It was the 65CE02 which had an on chip clock which you could send a trigger to stop, causing the MP to go into a suspended but wake-able state (and from 5v to 1.5v consumption). When the clock resumed via external trigger, so did the MP without having to go through its full start up cycle. They never did much with it oddly.

When I read the article what popped into mind was low consumption while doing nothing, which is what made me think of it. So now I've shown my age and made quite the ass of myself, but what else is /. for?

So not the same thing. Sorry for the ruccus :) Hey I'm amazed I even remembered it :P

of course

[EmbeddedJanitor (597831)]

There are probably more Linux boxes running on ARM than on x86.

ARM, followd by PowerPC, are the most common cores for embedded Linux and embedded Linux boxes far outnumber servers and desktops (where x86 rule).

Re:timing

[ScrewMaster (602015)]

The fact that the CPU itself has no master clock is absolutely irrelevant to timing applications. You can bet your bottom dollar that the processor will sink interrupts, and that there will be a timer/counter component to the chip. Timing won't be a problem.

Re:The next palm pilot?

[OrangeTide (124937)]

It theoretically should make a good chip for PDAs and cellphones. I think initially it will be used as a controller for automobiles though. Asynchronous chips are currently not that fast because the tools used to design them are incredibly new, but they are already very low power. I predict we'll have them all over the place in a couple years is all. Intel and AMD might already be considering (or may already have) used asynchronous logic in parts of their processors or support chipsets.

Basically a good asynchronous chip would draw almost no power while it's waiting for something (like I/O events from network, keyboard, timers, etc). And it would instantly ramp up and handle the event as fast as it possible could. The speed is generally a factor of voltage and temprature. It's how fast the gates can switch and perform interlocks under current conditions, rather than what rate a clock is driving everything.

It's going to be interesting to see what performance metric is used on these "clockless" chips by the industry and by the marketing/sales types. MIPS? FLOPS? SPECmark? not that MHz was ever a good benchmark, but things like MIPS is a lot easier to manipulate to make your product appear faster than your competitors.

Re:The next palm pilot?

[gabebear (251933)]

Responsiveness of a CPU is never really a problem, humans generally precieve anything that happens in less than 1/10th of a second as happening instantaniously. The only real problem with using this chip in a PDA is it isn't very fast, the article says the chip is comparable to a 77Mhz ARM9 which is several times slower than anything you'd find in a PDA today. I would love to see a Palm-OS PDA based around this chip because of it's EXTREMELY low power consumption; we could be looking at the same kind of bat

Re:my god, you people are stupid

[Theatetus (521747)]

Long live digg? I think you mean long live reddit, bitch!

Re:Overdoing it

[langelgjm (860756)]

I know nothing about microprocessor design, but a simple answer would be to have a temperature sensor attached to a voltage regulator. When the temperature gets too high, reduce the voltage, and consequently, the speed (that is, assuming the other few posts I skimmed were correct - always a toss-up on /.).

Synchronous vs. Asynchoronous

[chriso11 (254041)]

Most digital logic has at least one repeating signal called a clock, which is used to sequence the logical changes (e.g. from 1 to 0) in the circuit. By limiting changes of state to a periodic time, you can simplify a digital design. One of the major challenges in digital design (besides errors in logic) is dealing with timing related issues such as race conditions. Race conditions occur when a logical operation uses the results of earlier operations. Because of the finite speed of signals inside a chip, sometimes a signal arrives too late for a proper operation to occur. Such an error considered to be a race condition.

Clocks help by allowing the designer to effectively freeze the state of the logical circuit on a regular basis. This way, all the signals in a chip can propagate to where they are supposed to go, then the logical operations occur. This process repeats on every clock pulse.

The problems with using clocks are pretty significant, however. First, you need to add a lot of additional circuitry to implement a clock. Another problem is that generally, A LOT of changes happen on every clock tick, which means a large spike in electical current (because you need to use the electrical current to actually change the state of all of the digital circuits). This spike also causes what is known as noise in electronics, and with higher frequency circuits, the noise can actually cause interference with other unconnected electronics (this is known as EMI). And another problem with a clock is that you generally need to keep it running all of the time for it to be useful, which means using electrical power even when no changes are occurring.

So, the asynchronous CPU is a significant engineering feat. It is very difficult to design, but it is probably much smaller and more efficient than any equivalent clocked ARM core. That said, I wonder how do you actually evaluate the performance? With synchronous CPUs, it is a simply a function of the clock speed and architecture. In addition, all of these devices need to be tested so that they are guaranteed to work - I wonder how they do that.

Not really

[anirudhvr (923609)]

It's a regressive step if you look at the speed at which it can push things across. These days, the power consumed is as important an issue. Active research is going on in the area of Globally Asynchronous, Locally Synchronous (GALS, it's called ;) processors, where each module (like, say, the caches, execution units, reservation stations etc.) run their own clock (and hence its synchronous within the module), and communicate between each other using asynchronous protocols (known as delay insensitive protocols). Such a design greatly reduces the need for clock wiring which would greatly reduce area, reduce clock wiring, save power etc. (at the cost of some processing speed, of course). Google for Globally Asynchronous.. if interested.

You'd have to specify a specific benchmark...

[mbessey (304651)]

There's no easy answer. On a traditional clocked processor, each instruction takes a certain number of clock cycles. In the async case, everything just takes however long it takes. In fact, some arithmetic operations might take variable amounts of time depending on the value of the operands.

Given an equivalent process, layout technology, and number of transistors, an async design will be at least somewhat faster and vastly more power-efficient than a clocked design.

But none of those things are going to be equivalent in the real world - except possibly the process that ARM designs to. So comparisons will be difficult.